Datasheet

Rev. B | Page 32 of 44 | July 2013
ADSP-BF592
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 27 and Figure 20 describe SPI port slave operations.
Table 27. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
SPICHS
Serial Clock High Period 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
SPICLS
Serial Clock Low Period 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
SPICLK
Serial Clock Period 4 × t
SCLK
4 × t
SCLK
ns
t
HDS
Last SCK Edge to SPI_SS Not Asserted 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
SPITDS
Sequential Transfer Delay 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
SDSCI
SPI_SS Assertion to First SCK Edge 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
SSPID
Data Input Valid to SCK Edge (Data Input Setup) 1.6 1.6 ns
t
HSPID
SCK Sampling Edge to Data Input Invalid 2 1.6 ns
Switching Characteristics
t
DSOE
SPI_SS Assertion to Data Out Active 0 12 0 10.3 ns
t
DSDHI
SPI_SS Deassertion to Data High Impedance 0 11 0 9 ns
t
DDSPID
SCK Edge to Data Out Valid (Data Out Delay) 10 10 ns
t
HDSPID
SCK Edge to Data Out Invalid (Data Out Hold) 0 0 ns
Figure 20. Serial Peripheral Interface (SPI) Port—Slave Timing
t
SPICLK
t
HDS
t
SPITDS
t
SDSCI
t
SPICLS
t
SPICHS
t
DSOE
t
DDSPID
t
DDSPID
t
DSDHI
t
HDSPID
t
SSPID
t
DSDHI
t
HDSPID
t
DSOE
t
HSPID
t
SSPID
t
DDSPID
SPIxSS
(INPUT)
SPIxSCK
(INPUT)
SPIxMISO
(OUTPUT)
SPIxMOSI
(INPUT)
SPIxMISO
(OUTPUT)
SPIxMOSI
(INPUT)
CPHA = 1
CPHA = 0
t
HSPID