Datasheet

ADSP-BF592
Rev. B | Page 31 of 44 | July 2013
Serial Peripheral Interface (SPI) Port—Master Timing
Table 26 and Figure 19 describe SPI port master operations.
Table 26. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid to SCK Edge (Data Input Setup) 11.6 9.6 ns
t
HSPIDM
SCK Sampling Edge to Data Input Invalid –1.5 –1.5 ns
Switching Characteristics
t
SDSCIM
SPI_SELx low to First SCK Edge 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
SPICHM
Serial Clock High Period 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
SPICLM
Serial Clock Low Period 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
SPICLK
Serial Clock Period 4 × t
SCLK
– 1.5 4 × t
SCLK
– 1.5 ns
t
HDSM
Last SCK Edge to SPI_SELx High 2 × t
SCLK
– 2 2 × t
SCLK
– 1.5 ns
t
SPITDM
Sequential Transfer Delay 2 × t
SCLK
– 1.5 2 × t
SCLK
– 1.5 ns
t
DDSPIDM
SCK Edge to Data Out Valid (Data Out Delay) 0606ns
t
HDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold) –1 –1 ns
Figure 19. Serial Peripheral Interface (SPI) Port—Master Timing
t
SDSCIM
t
SPICLK
t
HDSM
t
SPITDM
t
SPICLM
t
SPICHM
t
HDSPIDM
t
HSPIDM
t
SSPIDM
SPIxSELy
(OUTPUT)
SPIxSCK
(OUTPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
CPHA = 1
CPHA = 0
t
DDSPIDM
t
HSPIDM
t
SSPIDM
t
HDSPIDM
t
DDSPIDM