Datasheet

Rev. B | Page 30 of 44 | July 2013
ADSP-BF592
Table 25. Serial Ports—Gated Clock Mode
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SDRI
Receive Data Setup Before TSCLKx 11.3 8.7 ns
t
HDRI
Receive Hold After TSCLKx 0 0 ns
Switching Characteristics
t
DDTI
Transmit Data Delay After TSCLKx 3 3 ns
t
HDTI
Transmit Data Hold After TSCLKx –1.8 –1.8 ns
t
DFTSCLKCNV
First TSCLKx edge delay after TFSx/TMR1 Low 0.5 × t
TSCLK
– 3 0.5 × t
TSCLK
– 3 ns
t
DCNVLTSCLK
TFSx/TMR1 High Delay After Last TSCLKx Edge t
TSCLK
– 3 t
TSCLK
– 3 ns
Figure 18. Serial Ports Gated Clock Mode
TSCLKx
(OUT)
GATED CLOCK MODE DATA RECEIVE
TFS/TMR
(OUT)
DTx
DELAY TIME DATA TRANSMIT
t
HDRI
t
SDRI
TSCLKx
(OUT)
TSCLKx
(OUT)
t
DDTI
t
HDTI
DRx
t
DFTSCLKCNV
t
DCNVLTSCLK
t
DCNVLTSCLK
t
DFTSCLKCNV