Datasheet

ADSP-BF592
Rev. B | Page 29 of 44 | July 2013
Table 24. Serial Ports—External Late Frame Sync
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Min Max Min Max Unit
Switching Characteristics
t
DDTLFSE
Data Delay from Late External TFSx
or External RFSx in multi-channel mode with MFD = 0
1, 2
12 10 ns
t
DTENLFSE
Data Enable from External RFSx in multi-channel mode with
MFD = 0
1, 2
00ns
1
When in multi-channel mode, TFSx enable and TFSx valid follow t
DTENLFSE
and t
DDTLFSE
.
2
If external RFSx/TFSx setup to RSCLKx/TSCLKx > t
SCLKE
/2 then t
DDTTE/I
and t
DTENE/I
apply, otherwise t
DDTLFSE
and t
DTENLFSE
apply.
Figure 17. Serial Ports — External Late Frame Sync
RSCLKx
RFSx
DTx
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
EXTERNAL RFSx IN MULTI-CHANNEL MODE
1ST BIT
t
DTENLFSE
t
DDTLFSE
TSCLKx
TFSx
DTx
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
LATE EXTERNAL TFSx
1ST BIT
t
DDTLFSE