Datasheet

Rev. B | Page 26 of 44 | July 2013
ADSP-BF592
Serial Ports
Table 21 through Table 25 and Figure 14 through Figure 18
describe serial port operations.
Table 21. Serial Ports—External Clock
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
SFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
33ns
t
HFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
33ns
t
SDRE
Receive Data Setup Before RSCLKx
1
33ns
t
HDRE
Receive Data Hold After RSCLKx
1
3.5 3 ns
t
SCLKEW
TSCLKx/RSCLKx Width 4.5 4.5 ns
t
SCLKE
TSCLKx/RSCLKx Period 2 × t
SCLK
2 × t
SCLK
ns
t
SUDTE
Start-Up Delay From SPORT Enable To First External TFSx
2
4 × t
TSCLKE
4 × t
TSCLKE
ns
t
SUDRE
Start-Up Delay From SPORT Enable To First External RFSx
2
4 × t
RSCLKE
4 × t
RSCLKE
ns
Switching Characteristics
t
DFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
3
10 10 ns
t
HOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
1
00ns
t
DDTE
Transmit Data Delay After TSCLKx
1
11 10 ns
t
HDTE
Transmit Data Hold After TSCLKx
1
00ns
1
Referenced to sample edge.
2
Verified in design but untested.
3
Referenced to drive edge.
Table 22. Serial Ports—Internal Clock
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
SFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
11.5 9.6 ns
t
HFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
–1.5 –1.5 ns
t
SDRI
Receive Data Setup Before RSCLKx
1
11.5 11.3 ns
t
HDRI
Receive Data Hold After RSCLKx
1
–1.5 –1.5 ns
Switching Characteristics
t
SCLKIW
TSCLKx/RSCLKx Width 7 8 ns
t
DFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
2
43ns
t
HOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
1
–2 –2 ns
t
DDTI
Transmit Data Delay After TSCLKx
1
43ns
t
HDTI
Transmit Data Hold After TSCLKx
1
–1.8 –1.5 ns
1
Referenced to sample edge.
2
Referenced to drive edge.