Datasheet

Rev. B | Page 24 of 44 | July 2013
ADSP-BF592
Parallel Peripheral Interface Timing
Table 20 and Figure 9 through Figure 13 describe parallel
peripheral interface operations.
Table 20. Parallel Peripheral Interface Timing
Parameter
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min Max Unit
Timing Requirements
t
PCLKW
PPI_CLK Width
1
t
SCLK
–1.5 t
SCLK
–1.5 ns
t
PCLK
PPI_CLK Period
1
2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
Timing Requirements—GP Input and Frame Capture Modes
t
PSUD
External Frame Sync Startup Delay
2
4 × t
PCLK
4 × t
PCLK
ns
t
SFSPE
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
6.7 6.7 ns
t
HFSPE
External Frame Sync Hold After PPI_CLK 1.8 1.6 ns
t
SDRPE
Receive Data Setup Before PPI_CLK 4.1 3.5 ns
t
HDRPE
Receive Data Hold After PPI_CLK 2 1.6 ns
Switching Characteristics—GP Output and Frame Capture Modes
t
DFSPE
Internal Frame Sync Delay After PPI_CLK 9.0 8.0 ns
t
HOFSPE
Internal Frame Sync Hold After PPI_CLK 1.7 1.7 ns
t
DDTPE
Transmit Data Delay After PPI_CLK 8.7 8.0 ns
t
HDTPE
Transmit Data Hold After PPI_CLK 2.3 1.9 ns
1
PPI_CLK frequency cannot exceed f
SCLK
/2.
2
The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words
guaranteed to be received correctly by the PPI peripheral.
Figure 9. PPI with External Frame Sync Timing
Figure 10. PPI GP Rx Mode with External Frame Sync Timing
PPI_CLK
PPI_FS1/2
t
PSUD
t
PCLK
t
SFSPE
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
t
HFSPE
t
HDRPE
t
SDRPE
t
PCLKW