Datasheet

Rev. B | Page 22 of 44 | July 2013
ADSP-BF592
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Clock and Reset Timing
Table 18 and Figure 7 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 8 to
Table 10, combinations of CLKIN and clock multipliers must
not select core/peripheral clocks in excess of the processor’s
instruction rate.
Table 18. Clock and Reset Timing
V
DDEXT
1.8 V Nominal V
DDEXT
2.5 V/3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
f
CKIN
CLKIN Period
1, 2, 3, 4
12 50 12 50 MHz
t
CKINL
CLKIN Low Pulse
1
10 10 ns
t
CKINH
CLKIN High Pulse
1
10 10 ns
t
WRST
RESET Asserted Pulse Width Low
5
11 × t
CKIN
11 × t
CKIN
ns
Switching Characteristic
t
BUFDLAY
CLKIN to CLKBUF
6
Delay 11 10 ns
1
Applies to PLL bypass mode and PLL non bypass mode.
2
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
VCO
, f
CCLK
, and f
SCLK
settings discussed in Table 8 on Page 17 through Table 10
on Page 17.
3
The t
CKIN
period (see Figure 7) equals 1/f
CKIN
.
4
If the DF bit in the PLL_CTL register is set, the minimum f
CKIN
specification is 24 MHz.
5
Applies after power-up sequence is complete. See Table 19 and Figure 8 for power-up reset timing.
6
The ADSP-BF592 processor does not have a dedicated CLKBUF pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or CLKOUT. This parameter applies
when EXTCLK is programmed to output CLKBUF.
Figure 7. Clock and Reset Timing
CLKIN
t
WRST
t
CKIN
t
CKINL
t
CKINH
t
BUFDLAY
t
BUFDLAY
RESET
CLKBUF