Datasheet

ADSP-BF592
Rev. B | Page 17 of 44 | July 2013
ADSP-BF592 Clock Related Operating Conditions
Table 8 describes the core clock timing requirements for the
ADSP-BF592 processor. Take care in selecting MSEL, SSEL, and
CSEL ratios so as not to exceed the maximum core clock and
system clock (see Table 10). Table 9 describes phase-locked loop
operating conditions.
Table 8. Core Clock (CCLK) Requirements
Parameter
Min V
DDINT
Nom V
DDINT
Max CCLK
Frequency Unit
f
CCLK
Core Clock Frequency (All Models) 1.33 V 1.400 V 400 MHz
Core Clock Frequency (Industrial/Commercial Models) 1.16 V 1.225 V 300 MHz
Core Clock Frequency (Industrial/Commercial Models) 1.10 V 1.150 V 250
1
MHz
1
See the Ordering Guide on Page 44.
Table 9. Phase-Locked Loop Operating Conditions
Parameter Min Max Unit
f
VCO
Voltage Controlled Oscillator (VCO) Frequency
(Non-Automotive Models)
72 Instruction Rate
1
MHz
Voltage Controlled Oscillator (VCO) Frequency
(Automotive Models)
84 Instruction Rate
1
MHz
1
See the Ordering Guide on Page 44.
Table 10. Maximum SCLK Conditions
Parameter
1
V
DDEXT
1.8 V/2.5 V/3.3 V Nominal Unit
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
1.16 V ) 100 MHz
CLKOUT/SCLK Frequency (V
DDINT
<1.16 V ) 80 MHz
1
f
SCLK
must be less than or equal to f
CCLK
.