Datasheet

ADSP-BF592
Rev. B | Page 15 of 44 | July 2013
PG10–GPIO/SPI1_MISO/PPI_D2 I/O GPIO/SPI1 Master In Slave Out/PPI Data 2
(This pin should always be pulled high through a 4.7 kΩ resistor if booting via
the SPI port.)
A
PG11–GPIO/SPI1_SSEL5
/PPI_D3 I/O GPIO/SPI1 Slave Select Enable 5/PPI Data 3 A
PG12–GPIO/SPI1_SSEL2
/PPI_D4/WAKEN2 I/O GPIO/SPI1 Slave Select Enable 2 Output/PPI Data 4/Wake Enable 2 A
PG13–GPIO/SPI1_SSEL1
/SPI1_SS/PPI_D5 I/O GPIO/SPI1 Slave Select Enable 1 Output/PPI Data 5/SPI1 Slave Select Input A
PG14–GPIO/SPI1_SSEL4
/PPI_D6/TACLK1 I/O GPIO/SPI1 Slave Select Enable 4/PPI Data 6/Timer 1 Auxiliary Clock Input A
PG15–GPIO/SPI1_SSEL6
/PPI_D7/TACLK2 I/O GPIO/SPI1 Slave Select Enable 6/PPI Data 7/Timer 2 Auxiliary Clock Input A
TWI
SCL I/O TWI Serial Clock (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I
2
C specification for the proper resistor
value.)
B
SDA I/O TWI Serial Data (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I
2
C specification for the proper resistor
value.)
B
JTAG Port
TCK I JTAG CLK
TDO O JTAG Serial Data Out A
TDI I JTAG Serial Data In
TMS I JTAG Mode Select
TRST
IJTAGReset
(This lead should be pulled low if the JTAG port is not used.)
EMU O Emulation Output
A
Clock
CLKIN I CLK/Crystal In
XTAL O Crystal Output
EXTCLK O External Clock Output pin/System Clock Output C
Mode Controls
RESET
I Reset
NMI
I Nonmaskable Interrupt
(Thisleadshouldbepulledhighwhennotused.)
BMODE2–0 I Boot Mode Strap 2–0
PPI_CLK I PPI Clock Input
External Regulator Control
PG
I Power Good indication
EXT_WAKE O Wake up Indication A
Power Supplies ALL SUPPLIES MUST BE POWERED
See Operating Conditions on Page 16.
V
DDEXT
PI/OPowerSupply
V
DDINT
P Internal Power Supply
GND G Ground for All Supplies (Back Side of LFCSP Package.)
Table 7. Signal Descriptions (Continued)
Signal Name Type Function
Driver
Type