Blackfin Embedded Processor ADSP-BF592 FEATURES PERIPHERALS Up to 400 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Accepts a wide range of supply voltages for internal and I/O operations, see Operating Conditions on Page 16 Off-chip voltage regulator interface 64-lead (9 mm × 9 mm) LFCSP package
ADSP-BF592 TABLE OF CONTENTS Features ................................................................. 1 Related Signal Chains ........................................... 13 Memory ................................................................ 1 Signal Descriptions ................................................. 14 Peripherals ............................................................. 1 Specifications ........................................................ 16 General Description .............
ADSP-BF592 GENERAL DESCRIPTION The ADSP-BF592 processor is a member of the Blackfin® family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dualMAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.
ADSP-BF592 head looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources.
ADSP-BF592 MEMORY ARCHITECTURE Custom ROM (Optional) The Blackfin processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory and I/O control registers, occupy separate sections of this common address space. See Figure 3.
ADSP-BF592 • Exceptions – Events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts – Events that occur asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction.
ADSP-BF592 initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error.
ADSP-BF592 General-Purpose Mode Descriptions DYNAMIC POWER MANAGEMENT The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. Three distinct submodes are supported: The processor provides five operating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation.
ADSP-BF592 Note that when a GPIO pin is used to trigger wake from deep sleep, the programmed wake level must linger for at least 10ns to guarantee detection.
ADSP-BF592 recommended. The two capacitors and the series resistor shown in Figure 4 fine tune phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 4 are typical values only. The capacitor values are dependent upon the crystal manufacturers’ load capacitance recommendations and the PCB physical layout. The resistor value depends on the drive level specified by the crystal manufacturer.
ADSP-BF592 BOOTING MODES • SPI0 master boot from flash (BMODE = 0x4) — In this mode SPI0 is configured to operate in master mode and to connect to 8-, 16-, 24-, or 32-bit addressable devices. The processor uses the PF8/SPI0_SSEL2 to select a single SPI EEPROM/flash device, submits a read command and successive address bytes (0×00) until a valid 8-, 16-, 24-, or 32bit addressable device is detected, and begins clocking data into the processor. Pull-up resistors are required on the SSEL and MISO pins.
ADSP-BF592 INSTRUCTION SET DESCRIPTION The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction.
ADSP-BF592 Middleware Packages Analog Devices separately offers middleware add-ins such as real time operating systems, file systems, USB stacks, and TCP/IP stacks. For more information see the following web pages: • www.analog.com/ucos3 • www.analog.com/ucfs • www.analog.com/ucusbd gather and process data or to apply system controls based on analysis of real-time phenomena.
ADSP-BF592 SIGNAL DESCRIPTIONS Signal definitions for the ADSP-BF592 processor are listed in Table 7. In order to maintain maximum function and reduce package size and pin count, some pins have dual, multiplexed functions. In cases where pin function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics. create a crystal oscillator circuit.
ADSP-BF592 Table 7.
ADSP-BF592 SPECIFICATIONS Specifications are subject to change without notice.
ADSP-BF592 ADSP-BF592 Clock Related Operating Conditions Table 8 describes the core clock timing requirements for the ADSP-BF592 processor. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock (see Table 10). Table 9 describes phase-locked loop operating conditions. Table 8.
ADSP-BF592 ELECTRICAL CHARACTERISTICS Parameter VOH VOH VOH VOL High Level Output Voltage High Level Output Voltage High Level Output Voltage Low Level Output Voltage VOLTWI Low Level Output Voltage IIH IIL IIHP IOZH IOZHTWI IOZL CIN IDDDEEPSLEEP7 High Level Input Current1 Low Level Input Current1 High Level Input Current JTAG2 Three-State Leakage Current3 Three-State Leakage Current4 Three-State Leakage Current3 Input Capacitance5 VDDINT Current in Deep Sleep Mode IDDSLEEP VDDINT Current in Sleep Mo
ADSP-BF592 Total Power Dissipation The ASF is combined with the CCLK frequency and VDDINT dependent data in Table 13 to calculate this part. The second part is due to transistor switching in the system clock (SCLK) domain, which is included in the IDDINT specification equation. Total power dissipation has two components: 1. Static, including leakage current 2.
ADSP-BF592 ABSOLUTE MAXIMUM RATINGS Characteristics table. Stresses greater than those listed in Table 14 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 16. Total Current Pin Groups–VDDEXT Groups Table 14.
ADSP-BF592 PACKAGE INFORMATION The information presented in Figure 6 and Table 17 provides details about the package branding for the ADSP-BF592 processor. For a complete listing of product availability, see Ordering Guide on Page 44. a ADSP-BF592 tppZccc vvvvvv.x n.n #yyww country_of_origin B Figure 6. Product Information on Package Table 17. Package Brand Information Brand Key ADSP-BF592 t pp Z ccc vvvvvv.x n.
ADSP-BF592 TIMING SPECIFICATIONS Specifications are subject to change without notice. Clock and Reset Timing Table 18 and Figure 7 describe clock and reset operations. Per the CCLK and SCLK timing specifications in Table 8 to Table 10, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of the processor’s instruction rate. Table 18.
ADSP-BF592 Table 19. Power-Up Reset Timing Parameter Min Max Unit Timing Requirements tRST_IN_PWR RESET Deasserted after the VDDINT, VDDEXT, and CLKIN Pins are Stable and within 3500 × tCKIN Specification tRST_IN_PWR RESET CLKIN V DD_SUPPLIES Figure 8. Power-Up Reset Timing Rev.
ADSP-BF592 Parallel Peripheral Interface Timing Table 20 and Figure 9 through Figure 13 describe parallel peripheral interface operations. Table 20. Parallel Peripheral Interface Timing VDDEXT = 1.8 V Max VDDEXT = 2.5 V/3.3 V Min Max Unit tSCLK –1.5 2 × tSCLK –1.5 tSCLK –1.5 2 × tSCLK –1.5 ns ns 4 × tPCLK 6.7 4 × tPCLK 6.7 ns ns 1.8 4.1 2 1.6 3.5 1.
ADSP-BF592 DATA DRIVEN / FRAME SYNC SAMPLED PPI_CLK tSFSPE tHFSPE tPCLKW tPCLK PPI_FS1/2 tDDTPE tHDTPE PPI_DATA Figure 11. PPI GP Tx Mode with External Frame Sync Timing FRAME SYNC DRIVEN DATA SAMPLED PPI_CLK tHOFSPE tDFSPE tPCLKW tPCLK PPI_FS1/2 tSDRPE tHDRPE PPI_DATA Figure 12. PPI GP Rx Mode with Internal Frame Sync Timing FRAME SYNC DRIVEN DATA DRIVEN tPCLK PPI_CLK tHOFSPE tDFSPE tPCLKW PPI_FS1/2 tDDTPE tHDTPE PPI_DATA Figure 13.
ADSP-BF592 Serial Ports Table 21 through Table 25 and Figure 14 through Figure 18 describe serial port operations. Table 21.
ADSP-BF592 DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE DRIVE EDGE SAMPLE EDGE SAMPLE EDGE tSCLKE tSCLKEW tSCLKIW RSCLKx RSCLKx tDFSE tDFSI tHOFSI tHOFSE RFSx (OUTPUT) RFSx (OUTPUT) tSFSI tHFSI RFSx (INPUT) tSFSE tHFSE tSDRE tHDRE RFSx (INPUT) tSDRI tHDRI DRx DRx DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE t SCLKEW TSCLKx tSCLKE TSCLKx tD FSI tDFSE tHOFSI tHOFSE TFSx (OUTPUT) TFS
ADSP-BF592 Table 23. Serial Ports—Enable and Three-State Min Parameter Switching Characteristics tDTENE Data Enable Delay from External TSCLKx1 tDDTTE Data Disable Delay from External TSCLKx1 tDTENI Data Enable Delay from Internal TSCLKx1 Data Disable Delay from Internal TSCLKx1 tDDTTI 1 VDDEXT 1.8V Nominal Max 0 0 tSCLK + 1 –2 DRIVE EDGE DRIVE EDGE TSCLKx tDTENE/I tDDTTE/I DTx Figure 16. Serial Ports — Enable and Three-State | Page 28 of 44 | tSCLK + 1 –2 tSCLK + 1 Referenced to drive edge.
ADSP-BF592 Table 24. Serial Ports—External Late Frame Sync Min Parameter Switching Characteristics tDDTLFSE Data Delay from Late External TFSx or External RFSx in multi-channel mode with MFD = 01, 2 tDTENLFSE Data Enable from External RFSx in multi-channel mode with 0 MFD = 01, 2 1 2 VDDEXT 1.8V Nominal Max 12 When in multi-channel mode, TFSx enable and TFSx valid follow tDTENLFSE and tDDTLFSE.
ADSP-BF592 Table 25. Serial Ports—Gated Clock Mode Parameter Timing Requirements tSDRI Receive Data Setup Before TSCLKx tHDRI Receive Hold After TSCLKx Switching Characteristics Transmit Data Delay After TSCLKx tDDTI tHDTI Transmit Data Hold After TSCLKx tDFTSCLKCNV First TSCLKx edge delay after TFSx/TMR1 Low tDCNVLTSCLK TFSx/TMR1 High Delay After Last TSCLKx Edge Min VDDEXT 1.8V Nominal Max 11.3 0 Unit 8.7 0 ns ns 3 3 –1.8 0.5 × tTSCLK – 3 tTSCLK – 3 –1.8 0.
ADSP-BF592 Serial Peripheral Interface (SPI) Port—Master Timing Table 26 and Figure 19 describe SPI port master operations. Table 26.
ADSP-BF592 Serial Peripheral Interface (SPI) Port—Slave Timing Table 27 and Figure 20 describe SPI port slave operations. Table 27.
ADSP-BF592 Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing The UART ports receive and transmit operations are described in the ADSP-BF59x Hardware Reference Manual. General-Purpose Port Timing Table 28 and Figure 21 describe general-purpose port operations. Table 28. General-Purpose Port Timing VDDEXT 1.8V/2.5 V/3.
ADSP-BF592 Timer Cycle Timing Table 29 and Figure 22 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz. Table 29. Timer Cycle Timing VDDEXT 2.5 V/3.3V Nominal Min Max Unit 1 × tSCLK 1 × tSCLK ns 1 × tSCLK 1 × tSCLK ns 10 –2 8 –2 ns ns VDDEXT 1.
ADSP-BF592 JTAG Test And Emulation Port Timing Table 31 and Figure 24 describe JTAG port operations. Table 31. JTAG Port Timing Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High System Inputs Setup Before TCK High1 tSSYS tHSYS System Inputs Hold After TCK High1 tTRSTW TRST Pulse Width2 (measured in TCK cycles) Switching Characteristics tDTDO TDO Delay from TCK Low tDSYS System Outputs Delay After TCK Low3 Min VDDEXT 1.
ADSP-BF592 OUTPUT DRIVE CURRENTS Figure 25 through Figure 33 show typical current-voltage characteristics for the output drivers of the ADSP-BF592 processor. 40 VDDEXT = 1.9V @ – 40°C VDDEXT = 3.0V @ – 40°C 100 VDDEXT = 3.3V @ 25°C 80 VDDEXT = 3.6V @ 105°C SOURCE CURRENT (mA) 60 40 VOH 20 20 VOH SOURCE CURRENT (mA) 120 VDDEXT = 1.8V @ 25°C VDDEXT = 1.7V @ 105°C 30 The curves represent the current drive capability of the output drivers.
ADSP-BF592 60 50 VDDEXT = 1.9V @ – 40°C 40 VDDEXT = 1.8V @ 25°C 30 VDDEXT = 1.7V @ 105°C 20 10 0 –10 –20 VOL –30 VDDEXT = 1.8V @ 25°C VDDEXT = 1.7V @ 105°C 40 SOURCE CURRENT (mA) SOURCE CURRENT (mA) VDDEXT = 1.9V @ – 40°C 20 VOH 0 –20 VOL –40 –40 –60 –50 0 0.5 1.0 0 1.5 0.5 1.0 1.5 SOURCE VOLTAGE (V) SOURCE VOLTAGE (V) Figure 33. Driver Type C Current (1.8V VDDEXT) Figure 30. Driver Type B Current (1.8V VDDEXT) TEST CONDITIONS 150 SOURCE CURRENT (mA) VDDEXT = 3.
ADSP-BF592 The time tENA_MEASURED is the interval from when the reference signal switches to when the output voltage reaches VTRIP(high) or VTRIP(low) and is shown below. • VDDEXT (nominal) = 1.8 V, VTRIP (high) is 1.05 V, VTRIP (low) is 0.75 V Capacitive Loading Output delays and holds are based on standard capacitive loads of an average of 6 pF on all pins (see Figure 36). VLOAD is equal to (VDDEXT)/2. • VDDEXT (nominal) = 2.5 V, VTRIP (high) is 1.5 V, VTRIP (low) is 1.
ADSP-BF592 18 9 16 8 tFALL tFALL 7 RISE AND FALL TIME (ns) RISE AND FALL TIME (ns) 14 tRISE 12 10 8 6 4 tFALL = 2.5V @ 25°C 2 6 tRISE 5 4 3 2 tFALL = 2.5V @ 25°C 1 tRISE = 2.5V @ 25°C tRISE = 2.5V @ 25°C 0 0 0 50 100 150 200 250 0 50 LOAD CAPACITANCE (pF) Figure 38. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2.5V VDDEXT) 150 250 7 14 tFALL 6 tFALL 12 RISE AND FALL TIME (ns) tRISE 10 8 6 4 2 5 tRISE 4 3 2 1 tFALL = 3.3V @ 25°C tFALL = 3.
ADSP-BF592 ENVIRONMENTAL CONDITIONS To determine the junction temperature on the application printed circuit board use: T J = T CASE + JT P D where: TJ = junction temperature (°C) TCASE = case temperature (°C) measured by customer at top center of package. JT = from Table 32 PD = power dissipation (see Total Power Dissipation on Page 19 for the method to calculate PD) Table 32.
ADSP-BF592 64-LEAD LFCSP LEAD ASSIGNMENT Table 33 lists the LFCSP leads by signal mnemonic. Table 34 lists the LFCSP by lead number. Table 33. 64-Lead LFCSP Lead Assignment (Alphabetical by Signal) Signal BMODE0 BMODE1 BMODE2 EXTCLK/SCLK CLKIN EMU EXT_WAKE GND NMI PF0 PF1 PF2 PF3 PF4 PF5 PF6 Lead No. 29 28 27 57 61 19 51 30 54 63 64 1 2 4 5 6 Signal PF7 PF8 PF9 PF10 PF11 PF12 PF13 PF14 PF15 PG PG0 PG1 PG2 PG3 PG4 PG5 Lead No.
ADSP-BF592 Figure 43 shows the top view of the LFCSP lead configuration. Figure 44 shows the bottom view of the LFCSP lead configuration. PIN 64 PIN 49 PIN 1 PIN 48 PIN 1 INDICATOR ADSP-BF592 64-LEAD LFCSP TOP VIEW PIN 16 PIN 33 PIN 17 PIN 32 Figure 43. 64-Lead LFCSP Lead Configuration (Top View) PIN 49 PIN 64 PIN 48 PIN 1 ADSP-BF592 64-LEAD LFCSP BOTTOM VIEW GND PAD (PIN 65) PIN 1 INDICATOR PIN 33 PIN 16 PIN 32 PIN 17 Figure 44. 64-Lead LFCSP Lead Configuration (Bottom View) Rev.
ADSP-BF592 OUTLINE DIMENSIONS Dimensions in Figure 45 are shown in millimeters. 0.60 MAX 9.00 BSC SQ 0.60 MAX 48 64 49 1 PIN 1 INDICATOR PIN 1 INDICATOR 8.75 BSC SQ TOP VIEW 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 0.80 MAX 0.65 TYP 12° MAX SEATING PLANE 0.30 0.23 0.18 33 32 17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE LEAD ASSIGNMENT AND SIGNAL DESCRIPTIONS SECTIONS OF THIS DATA SHEET. 0.05 MAX 0.02 NOM 0.20 REF Figure 45.
ADSP-BF592 AUTOMOTIVE PRODUCTS The ADSP-BF592 is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models and designers should review the product specifications section of this data sheet carefully. Only the automotive grade products shown in Table 35 are available for use in automotive applications.
