Datasheet

ADSP-BF561
writing the appropriate values into the Interrupt Assignment Table 2. System Interrupt Controller (SIC) (Continued)
Registers (SIC_IAR7–0). Table 2 describes the inputs into the
SIC and the default mappings into the CEC.
Table 2. System Interrupt Controller (SIC)
Peripheral Interrupt Event
PLL Wakeup IVG7
DMA1 Error (Generic) IVG7
DMA2 Error (Generic) IVG7
IMDMA Error IVG7
PPI0 Error IVG7
PPI1 Error IVG7
SPORT0 Error IVG7
SPORT1 Error IVG7
SPI Error IVG7
UART Error IVG7
Reserved IVG7
DMA1 Channel 0 Interrupt (PPI0) IVG8
DMA1 Channel 1 Interrupt (PPI1) IVG8
DMA1 Channel 2 Interrupt IVG8
DMA1 Channel 3 Interrupt IVG8
DMA1 Channel 4 Interrupt IVG8
DMA1 Channel 5 Interrupt IVG8
DMA1 Channel 6 Interrupt IVG8
DMA1 Channel 7 Interrupt IVG8
DMA1 Channel 8 Interrupt IVG8
DMA1 Channel 9 Interrupt IVG8
DMA1 Channel 10 Interrupt IVG8
DMA1 Channel 11 Interrupt IVG8
DMA2 Channel 0 Interrupt (SPORT0 Rx) IVG9
DMA2 Channel 1 Interrupt (SPORT0 Tx) IVG9
DMA2 Channel 2 Interrupt (SPORT1 Rx) IVG9
DMA2 Channel 3 Interrupt (SPORT1 Tx) IVG9
DMA2 Channel 4 Interrupt (SPI) IVG9
DMA2 Channel 5 Interrupt (UART Rx) IVG9
DMA2 Channel 6 Interrupt (UART Tx) IVG9
DMA2 Channel 7 Interrupt IVG9
DMA2 Channel 8 Interrupt IVG9
DMA2 Channel 9 Interrupt IVG9
DMA2 Channel 10 Interrupt IVG9
DMA2 Channel 11 Interrupt IVG9
Timer0 Interrupt IVG10
Timer1 Interrupt IVG10
Timer2 Interrupt IVG10
Timer3 Interrupt IVG10
Timer4 Interrupt IVG10
Timer5 Interrupt IVG10
Timer6 Interrupt IVG10
Rev. E | Page 7 of 64 | September 2009
Default
Mapping
Peripheral Interrupt Event
Timer7 Interrupt IVG10
Timer8 Interrupt IVG10
Timer9 Interrupt IVG10
Timer10 Interrupt IVG10
Timer11 Interrupt IVG10
Programmable Flags 15–0 Interrupt A IVG11
Programmable Flags 15–0 Interrupt B IVG11
Programmable Flags 31–16 Interrupt A IVG11
Programmable Flags 31–16 Interrupt B IVG11
Programmable Flags 47–32 Interrupt A IVG11
Programmable Flags 47–32 Interrupt B IVG11
DMA1 Channel 12/13 Interrupt IVG8
(Memory DMA/Stream 0)
DMA1 Channel 14/15 Interrupt IVG8
(Memory DMA/Stream 1)
DMA2 Channel 12/13 Interrupt IVG9
(Memory DMA/Stream 0)
DMA2 Channel 14/15 Interrupt IVG9
(Memory DMA/Stream 1)
IMDMA Stream 0 Interrupt IVG12
IMDMA Stream 1 Interrupt IVG12
Watchdog Timer Interrupt IVG13
Reserved IVG7
Reserved IVG7
Supplemental Interrupt 0 IVG7
Supplemental Interrupt 1 IVG7
Default
Mapping
Event Control
The ADSP-BF561 provides the user with a very flexible mecha-
nism to control the processing of events. In the CEC, three
registers are used to coordinate and control events. Each of the
registers is 16 bits wide, while each bit represents a particular
event class.
• CEC Interrupt Latch Register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
may also be written to clear (cancel) latched events. This
register may be read while in supervisor mode and may
only be written while in supervisor mode when the corre-
sponding IMASK bit is cleared.
• CEC Interrupt Mask Register (IMASK) – The IMASK reg-
ister controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event,
thereby preventing the processor from servicing the event