Datasheet

ADSP-BF561
Timer Cycle Timing
Table 30 and Figure 27 describe timer expired operations. The
input signal is asynchronous in width capture mode and exter-
nal clock mode and has an absolute maximum input frequency
of f
SCLK
/2 MHz.
Table 30. Timer Cycle Timing
Parameter Min Max Unit
Timing Characteristics
t
WL
Timer Pulse Width Input Low
1
(Measured in SCLK Cycles)
t
WH
Timer Pulse Width Input High
1
(Measured in SCLK Cycles)
Switching Characteristic
t
HTO
Timer Pulse Width Output
2
(Measured in SCLK Cycles)
1
1
1 (2
32
–1)
SCLK
SCLK
SCLK
1
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPIxCLK input pins in PWM output mode.
2
The minimum time for t
HTO
is one cycle, and the maximum time for t
HTO
equals (2
32
–1) cycles.
CLKOUT
TMRx
(PWM OUTPUT MODE)
t
HTO
TMRx
(WIDTH CAPTURE AND
EXTERNAL CLOCK MODES)
t
WL
t
WH
Figure 27. Timer PWM_OUT Cycle Timing
Rev. E | Page 39 of 64 | September 2009