Datasheet

ADSP-BF561
Serial Peripheral Interface (SPI) Port—
Slave Timing
Table 28 and Figure 24 describe SPI port slave operations.
Table 28. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter Min Max Unit
Timing Requirements
t
SPICHS
Serial Clock High Period 2 × t
SCLK
– 1.5 ns
t
SPICLS
Serial Clock Low Period 2 × t
SCLK
– 1.5 ns
t
SPICLK
Serial Clock Period 4 × t
SCLK
ns
t
HDS
Last SCK Edge to SPISS Not Asserted 2 × t
SCLK
– 1.5 ns
t
SPITDS
Sequential Transfer Delay 2 × t
SCLK
– 1.5 ns
t
SDSCI
SPISS Assertion to First SCK Edge 2 × t
SCLK
– 1.5 ns
t
SSPID
Data Input Valid to SCK Edge (Data Input Setup) 1.6 ns
t
HSPID
SCK Sampling Edge to Data Input Invalid 1.6 ns
Switching Characteristics
t
DSOE
SPISS Assertion to Data Out Active 0 8 ns
t
DSDHI
SPISS Deassertion to Data High Impedance 0 8 ns
t
DDSPID
SCK Edge to Data Out Valid (Data Out Delay) 0 10 ns
t
HDSPID
SCK Edge to Data Out Invalid (Data Out Hold) 0 10 ns
SPIDS
(INPUT)
SPICLK
(CP = 0)
(INPUT)
SPICLK
(CP = 1)
(INPUT)
MISO
(OUTPUT)
CPHASE = 1
MOSI
(INPUT)
MISO
(OUTPUT)
CPHASE = 0
MOSI
(INPUT)
t
SPICHS
t
SPICLS
t
SPICLKS
t
HDS
t
SDPPW
t
SDSCO
t
SPICLS
t
SPICHS
t
DSOE
t
DDSPIDS
t
DDSPIDS
t
DSDHI
t
HDSPIDS
t
HSPIDS
t
SSPIDS
MSB VALID
LSB VALIDMSB VALID
t
SSPIDS
LSB
LSB
MSB
MSB
t
DSDHI
t
DDSPIDS
t
DSOV
t
HSPIDS
t
SSPIDS
t
HDSPIDS
LSB VALID
Figure 24. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. E | Page 36 of 64 | September 2009