Datasheet

ADSP-BF561
DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE
t
HOFSIR
t
HFSI
t
HDRI
t
SCLKIW
t
DFSIR
t
SFSI
t
SDRI
RSCLKx
RSCLKx
RFSx
RFSx
DRx
DRx
t
HOFSE
t
HFSE
t
HDRE
t
SCLKW
t
DFSE
t
SFSE
t
SDRE
NOTES
1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE
t
HFSI
t
DDTI
t
HOFSI
t
HDTI
t
SFSI
t
DFSI
t
SCLKIW
TSCLKx
TSCLKx
TFSx
TFSx
DTx
DTx
t
HOFSE
t
HFSE
t
HDTE
t
DDTE
t
DFSE
t
SFSE
t
SCLKW
Figure 20. Serial Ports
TSCLKx
(INPUT)
TFSx
(INPUT)
RFSx
(INPUT)
RSCLKx
(INPUT)
t
SUDTE
t
SUDRE
SPORT
ENABLED
Figure 21. Serial Port Start Up with External Clock and Frame Sync
Rev. E | Page 33 of 64 | September 2009