Datasheet

ADSP-BF561
DATA
DRIVING/
FRAME
SYNC
SAMPLING
EDGE
DATA
DRIVING/
FRAME
SYNC
SAMPLING
EDGE
t
HDTPE
t
DDTPE
POLS = 0
POLS = 0
POLC = 0
POLS = 1
POLS = 1
POLC = 1
t
HFSPE
t
SFSPE
PPIxCLK
PPIxCLK
PPIxSYNC1
PPIxSYNC2
PPIx_DATA
Figure 19. PPI GP Tx Mode with External Frame Sync Timing (Bit 4 of PLL_CTL Set)
Rev. E | Page 31 of 64 | September 2009