Datasheet

ADSP-BF561
Parallel Peripheral Interface Timing
Table 22, and Figure 14 through Figure 17 on Page 30, describe If bit 4 of the PLL_CTL register is set, then Figure 18 on Page 30
default Parallel Peripheral Interface operations. and Figure 19 on Page 31 apply.
Table 22. Parallel Peripheral Interface Timing
Parameter Min Max Unit
Timing Requirements
t
PCLKW
PPIxCLK Width
1
t
PCLK
PPIxCLK Period
1
t
SFSPE
External Frame Sync Setup Before PPIxCLK
t
HFSPE
External Frame Sync Hold After PPIxCLK
t
SDRPE
Receive Data Setup Before PPIxCLK
t
HDRPE
Receive Data Hold After PPIxCLK
Switching Characteristics
t
DFSPE
Internal Frame Sync Delay After PPIxCLK
t
HOFSPE
Internal Frame Sync Hold After PPIxCLK
t
DDTPE
Transmit Data Delay After PPIxCLK
t
HDTPE
Transmit Data Hold After PPIxCLK
5.0
13.3
4.0
1.0
3.5
2.0
8.0
1.7
8.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
For PPI modes that use an internally generated frame sync, the PPIxCLK frequency cannot exceed f
SCLK
/2. For modes with no frame syncs or external frame syncs, PPIxCLK
cannot exceed 75 MHz and f
SCLK
should be equal to or greater than PPIxCLK.
FRAME
SYNC IS
DATA0
DRIVEN
IS
OUT
SAMPLED
t
SDRPE
t
HDRPE
POLS = 0
POLS = 0
POLC = 0
POLS = 1
POLS = 1
POLC = 1
t
DFSPE
t
HOFSPE
PPIxCLK
PPIxCLK
PPIxSYNC1
PPIxSYNC2
PPIx_DATA
Figure 14. PPI GP Rx Mode with Internal Frame Sync Timing (Default)
Rev. E | Page 28 of 64 | September 2009