Datasheet

ADSP-BF561
SDRAM Interface Timing
Table 20. SDRAM Interface Timing
Parameter Min Max Unit
Timing Requirements
t
SSDAT
DATA Setup Before CLKOUT
t
HSDAT
DATA Hold After CLKOUT
Switching Characteristics
t
DCAD
Command, ADDR, Data Delay After CLKOUT
1
t
HCAD
Command, ADDR, Data Hold After CLKOUT
1
t
DSDAT
Data Disable After CLKOUT
t
ENSDAT
Data Enable After CLKOUT
t
SCLK
CLKOUT Period
t
SCLKH
CLKOUT Width High
t
SCLKL
CLKOUT Width Low
1.5
0.8
0.8
1.0
7.5
2.5
2.5
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Command pins include: SRAS, SCAS, SWE, SDQM, SMS3–0, SA10, SCKE.
SDCLK
DATA (IN)
DATA (OUT)
CMND ADDR
(OUT)
t
SDCLKH
t
SDCLKL
t
HSDAT
t
SSDAT
t
HCAD
t
DCAD
t
ENSDAT
t
DCAD
t
DSDAT
t
HCAD
t
SDCLK
Figure 12. SDRAM Interface Timing
Rev. E | Page 26 of 64 | September 2009