Datasheet

ADSP-BF561
Asynchronous Memory Write Cycle Timing
Table 19. Asynchronous Memory Write Cycle Timing
Parameter Min Max Unit
Timing Requirements
t
SARDY
ARDY Setup Before CLKOUT
t
HARDY
ARDY Hold After CLKOUT
Switching Characteristics
t
DDAT
DATA31–0 Disable After CLKOUT
t
ENDAT
DATA31–0 Enable After CLKOUT
t
DO
Output Delay After CLKOUT
1
t
HO
Output Hold After CLKOUT
1
4.0
0.0
1.0
0.8
6.0
6.0
ns
ns
ns
ns
ns
ns
1
Output pins include AMS3–0, ABE3–0, ADDR25–2, DATA31–0, AOE, AWE.
t
DO
t
ENDAT
CLKOUT
AMSx
ABE1–0
ABE, ADDRESS
t
HO
WRITE DATA
t
DDAT
DATA15–0
AWE
t
SARDY
t
HARDY
SETUP
2CYCLES
PROGRAMMED WRITE
ACCESS 2 CYCLES
ACCESS
EXTENDED
1CYCLE
HOLD
1CYCLE
ARDY
ADDR19–1
t
HO
t
SARDY
t
DO
Figure 11. Asynchronous Memory Write Cycle Timing
Rev. E | Page 25 of 64 | September 2009