Datasheet

ADSP-BF561
Asynchronous Memory Read Cycle Timing
Table 18. Asynchronous Memory Read Cycle Timing
Parameter Min Max Unit
Timing Requirements
t
SDAT
DATA31 –0 Setup Before CLKOUT
t
HDAT
DATA31–0 Hold After CLKOUT
t
SARDY
ARDY Setup Before CLKOUT
t
HARDY
ARDY Hold After CLKOUT
Switching Characteristics
t
DO
Output Delay After CLKOUT
1
t
HO
Output Hold After CLKOUT
1
2.1
0.8
4.0
0.0
6.0
0.8
ns
ns
ns
ns
ns
ns
1
Output pins include AMS3–0, ABE3–0, ADDR25–2, AOE, ARE.
t
DO
t
SDAT
CLKOUT
AMSx
ABE1–0
t
HO
ABE, ADDRESS
READ
t
HDAT
DATA15–0
AOE
t
DO
t
SARDY
t
HARDY
ACCESS EXTENDED
3CYCLES
1CYCLE
ARE
t
HARDY
ARDY
ADDR19–1
SETUP
2CYCLES
PROGRAMMED READ ACCESS
4CYCLES
t
HO
t
SARDY
Figure 10. Asynchronous Memory Read Cycle Timing
Rev. E | Page 24 of 64 | September 2009