Datasheet

ADSP-BF561
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 16 and Figure 8 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 22, combinations of
CLKIN and clock multipliers must not result in core/system
clocks exceeding the maximum limits allowed for the processor,
including system clock restrictions related to supply voltage.
Table 16. Clock and Normal Reset Timing
Parameter Min Max Unit
Timing Requirements
t
CKIN
CLKIN (to PLL) Period
1, 2, 3
t
CKINL
CLKIN Low Pulse
t
CKINH
CLKIN High Pulse
t
WRST
RESET Asserted Pulse Width Low
4
25.0
10.0
10.0
11 × t
CKIN
100.0 ns
ns
ns
ns
1
If DF bit in PLL_CTL register is set t
CLKIN
is divided by two before going to PLL, then the t
CLKIN
maximum period is 50 ns and the t
CLKIN
minimum period is 12.5 ns.
2
Applies to PLL bypass mode and PLL nonbypass mode.
3
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
VCO
, f
CCLK
, and f
SCLK
settings discussed in Table 9 on Page 20 through Table 12
on Page 21.
4
Applies after power-up sequence is complete. See Table 17 and Figure 9 for power-up reset timing.
RESET
CLKIN
t
CKINH
t
CKINL
t
WRST
t
CKIN
Figure 8. Clock and Normal Reset Timing
Table 17. Power-Up Reset Timing
Parameter Min Max Unit
Timing Requirements
t
RST _ IN _ PWR
RESET Deasserted after the V
DDINT
, V
DDEXT
, and CLKIN Pins are Stable and Within
Specification
3500 × t
CKIN
μs
RESET
CLKIN,
V
DDINT,
V
DDEXT
t
RST_IN_PWR
Figure 9. Power-Up Reset Timing
Rev. E | Page 23 of 64 | September 2009