Datasheet

ADSP-BF561
Table 11. Phase-Locked Loop Operating Conditions
Parameter Min Max Unit
Voltage Controlled Oscillator (VCO) Frequency 50 Maximum f
CCLK
MHz
Table 12. System Clock (SCLK) Requirements
Parameter
1
Max V
DDEXT
= 2.5V/3.3V Unit
f
SCLK
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
≥ 1.14 V)
CLKOUT/SCLK Frequency (V
DDINT
< 1.14 V)
133
2
100
MHz
MHz
1
t
SCLK
(= 1/f
SCLK
) must be greater than or equal to t
CCLK
.
2
Rounded number. Guaranteed to t
SCLK
= 7.5 ns. See Table 20 on Page 26.
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Min Typical Max Unit
V
OH
High Level Output Voltage
1
V
DDEXT
= 3.0 V, I
OH
= –0.5 mA 2.4 V
V
OL
Low Level Output Voltage
1
V
DDEXT
= 3.0 V, I
OL
= 2.0 mA 0.4 V
I
IH
High Level Input Current
2
V
DDEXT
= Maximum, V
IN
= V
DD
Maximum 10.0 μA
I
IHP
High Level Input Current JTAG
3
V
DDEXT
= Maximum, V
IN
= V
DD
Maximum 50.0 μA
I
IL
4
Low Level Input Current
2
V
DDEXT
= Maximum, V
IN
= 0 V 10.0 μA
I
OZH
Three-State Leakage Current
5
V
DDEXT
= Maximum, V
IN
= V
DD
Maximum 10.0 μA
I
OZL
4
Three-State Leakage Current
5
V
DDEXT
= Maximum, V
IN
= 0 V 10.0 μA
C
IN
Input Capacitance
6
f
IN
= 1 MHz, T
AMBIENT
= 25°C, V
IN
= 2.5 V 4 8
7
pF
I
DDHIBERNATE
8
V
DDEXT
Current in Hibernate Mode CLKIN=0 MHz, V
DDEXT
= 3.65 V with Voltage Regulator Off
(V
DDINT
= 0 V)
50 μA
I
DDDEEPSLEEP
9
V
DDINT
Current in Deep Sleep Mode V
DDINT
= 0.8 V, T
JUNCTION
= 25°C 70 mA
I
DD _ TYP
9, 10
V
DDINT
Current V
DDINT
= 0.8 V, f
CCLK
= 50 MHz, T
JUNCTION
= 25°C 127 mA
I
DD _ TYP
9, 10
V
DDINT
Current V
DDINT
= 1.25 V, f
CCLK
= 500 MHz, T
JUNCTION
= 25°C 660 mA
I
DD _ TYP
9, 10
V
DDINT
Current V
DDINT
= 1.35 V, f
CCLK
= 600 MHz, T
JUNCTION
= 25°C 818 mA
1
Applies to output and bidirectional pins.
2
Applies to input pins except JTAG inputs.
3
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
4
Absolute value.
5
Applies to three-statable pins.
6
Applies to all signal pins.
7
Guaranteed, but not tested.
8
CLKIN must be tied to V
DDEXT
or GND during hibernate.
9
Maximum current drawn. See Estimating Power for ADSP-BF561 Blackfin Processors (EE-293) on the Analog Devices website (www.analog.com)—use site search on “EE-293”.
10
Both cores executing 75% dual MAC, 25% ADD instructions with moderate data bus activity.
System designers should refer to Estimating Power for the
ADSP-BF561 (EE-293), which provides detailed information for
optimizing designs for lowest power. All topics discussed in this
section are described in detail in EE-293. Total power dissipa-
tion has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. Electrical Characteristics on Page 21 shows the
current dissipation for internal circuitry (V
DDINT
).
Rev. E | Page 21 of 64 | September 2009