Datasheet

ADSP-BF561
TABLE OF CONTENTS
Features ................................................................. 1
Peripherals ............................................................. 1
Table of Contents ..................................................... 2
Revision History ...................................................... 2
General Description ................................................. 3
Portable Low Power Architecture ............................. 3
Blackfin Processor Core .......................................... 3
Memory Architecture ............................................ 4
DMA Controllers .................................................. 8
Watchdog Timer .................................................. 8
Timers ............................................................... 9
Serial Ports (SPORTs) ............................................ 9
Serial Peripheral Interface (SPI) Port ......................... 9
UART Port .......................................................... 9
Programmable Flags (PFx) .................................... 10
Parallel Peripheral Interface ................................... 10
Dynamic Power Management ................................ 11
Voltage Regulation .............................................. 12
Clock Signals ..................................................... 13
Booting Modes ................................................... 14
Instruction Set Description ................................... 14
Development Tools ............................................. 15
REVISION HISTORY
9/09—Rev. D to Rev. E
Correct all outstanding document errata.
Revised Figure 5 .....................................................................13
Added 533 MHz operation Table 10 .................................. 20
Removed reference to 1.8 V operation Table 12 ...............21
Added Table 17 and Figure 9 Power-Up Reset Timing ....23
Removed references to T
J
from t
SCLK
parameter
Table 20 ................................................................................... 26
Added new SPORT timing parameters and diagram
Table 23 ................................................................................... 32
Figure 21 .................................................................................33
Designing an Emulator-Compatible Processor Board ... 16
Related Documents .............................................. 16
Pin Descriptions .................................................... 17
Specifications ........................................................ 20
Operating Conditions ........................................... 20
Electrical Characteristics ....................................... 21
Absolute Maximum Ratings ................................... 22
Package Information ............................................ 22
ESD Sensitivity ................................................... 22
Timing Specifications ........................................... 23
Output Drive Currents ......................................... 41
Power Dissipation
............................................... 42
Test Conditions .................................................. 42
Environmental Conditions .................................... 44
256-Ball CSP_BGA (17 mm) Ball Assignment ............... 46
256-Ball CSP_BGA (12 mm) Ball Assignment ............... 51
297-Ball PBGA Ball Assignment ................................. 56
Outline Dimensions ................................................ 61
Surface-Mount Design .......................................... 63
Automotive Products .............................................. 63
Ordering Guide ..................................................... 63
Rev. E | Page 2 of 64 | September 2009