Datasheet

ADSP-BF561
The time for the voltage on the bus to decay by ΔV is dependent
14
on the capacitive load C
L
and the load current I
L
. This decay time
can be approximated by the equation:
12
RISE TIME
FALL TIME
RISE AND FALL TIME ns (10% to 90%)
t
DECAY
= (C
L
ΔV) ⁄ I
L
The time t
DECAY
is calculated with test loads C
L
and I
L
, and with
ΔV equal to 0.5 V for V
DDEXT
(nominal) = 2.5 V/3.3 V.
The time t
DIS _ MEASURED
is the interval from when the reference sig-
nal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
10
8
6
4
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose ΔV
to be the difference between the ADSP-BF561 processor’s out-
put voltage and the input threshold for the device requiring the
hold time. C
L
is the total bus capacitance (per data line), and I
L
is
the total leakage or three-state current (per data line). The hold
time will be t
DECAY
plus the various output disable times as speci-
fied in the Timing Specifications on Page 23 (for example t
DSDAT
for an SDRAM write cycle as shown in SDRAM Interface Tim-
ing on Page 26).
2
0
0 50 100 150 200 250
LOAD CAPACITANCE (pF)
Figure 40. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at V
DDEXT
(min)
12
RISE TIME
FALL TIME
RISE AND FALL TIME ns (10% to 90%)
10
8
6
4
2
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS DRIVING
V
OH
(MEASURED)   V
V
OL
(MEASURED) + V
t
DIS_MEASURED
V
OH
(MEASURED)
V
OL
(MEASURED)
V
TRIP
(HIGH)
OUTPUT STOPS DRIVING
t
ENA
t
DECAY
t
ENA_MEASURED
t
TRIP
V
TRIP
(LOW)
V
OH
(MEASURED)
0
0 50 100 150 200 250
V
OL
(MEASURED)
LOAD CAPACITANCE (pF)
Figure 41. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver A at V
DDEXT
(max)
12
RISE TIME
FALL TIME
HIGH IMPEDANCE STATE
Figure 38. Output Enable/Disable
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 39). V
LOAD
is 1.5 V for V
DDEXT
(nomi-
nal) = 2.5 V/3.3 V. Figure 40 through Figure 47 on Page 44 show
how output rise time varies with capacitance. The delay and
hold specifications given should be derated by a factor derived
RISE AND FALL TIME ns (10% to 90%)
10
8
6
4
from these figures. The graphs in these figures may not be linear
2
outside the ranges shown.
0
0 50 100 150 200 250
50 
TO
LOAD CAPACITANCE (pF)
OUTPUT
V
LOAD
PIN
Figure 42. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver B at V
DDEXT
(min)
30pF
Figure 39. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Rev. E | Page 43 of 64 | September 2009