Datasheet

ADSP-BF561
FRAME
DATA0 IS
SYNC IS
DRIVEN
SAMPLED
OUT
t
HDTPE
t
DDTPE
POLS = 0
POLS = 0
POLC = 1
POLS = 1
POLS = 1
POLC = 0
t
HFSPE
t
SFSPE
PPIx_DATA
PPIxCLK
PPIxCLK
PPxSYNC1
PPIxSYNC2
DATA0
Figure 17. PPI GP Tx Mode with External Frame Sync Timing (Default)
DATA DATA
SAMPLING/ SAMPLING/
FRAME FRAME
SYNC SYNC
SAMPLING SAMPLING
EDGE EDGE
POLS = 0
POLS = 0
POLC = 0
POLS = 1
POLS = 1
POLC = 1
t
HFSPE
t
SFSPE
PPIxCLK
PPIxCLK
PPIxSYNC1
PPIxSYNC2
t
SDRPE
t
HDRPE
PPIx_DATA
Figure 18. PPI GP Rx Mode with External Frame Sync Timing (Bit 4 of PLL_CTL Set)
Rev. E | Page 30 of 64 | September 2009