Datasheet

ADSP-BF561
SPECIFICATIONS
Component specifications are subject to change without notice.
OPERATING CONDITIONS
Parameter Conditions Min Nominal Max Unit
V
DDINT
Internal Supply Voltage
1
Non automotive 500 MHz and 533 MHz speed grade models
2
0.8 1.25 1.375 V
V
DDINT
Internal Supply Voltage
3
600 MHz speed grade models
2
0.8 1.35 1.4185 V
V
DDINT
Internal Supply Voltage
3
Automotive grade models
2
0.95 1.25 1.375 V
V
DDEXT
External Supply Voltage Non automotive grade models
2
2.25 2.5, or 3.3 3.6 V
V
DDEXT
External Supply Voltage Automotive grade models
2
2.7 3.3 3.6 V
V
IH
High Level Input Voltage
4, 5
2.0 3.6 V
V
IL
Low Level Input Voltage
5
–0.3 +0.6 V
T
J
Junction Temperature 256-Ball CSP_BGA (12 mm × 12 mm) @ T
AMBIENT
= 0°C to +70°C 0 +105 °C
T
J
Junction Temperature 256-Ball CSP_BGA (17 mm × 17 mm) @ T
AMBIENT
= 0°C to +70°C 0 +95 °C
T
J
Junction Temperature 256-Ball CSP_BGA (17 mm × 17 mm) @ T
AMBIENT
=–40°C to +85°C –40 +115 °C
T
J
Junction Temperature 297-Ball PBGA @ T
AMBIENT
= 0°C to +70°C 0 +95 °C
T
J
Junction Temperature 297-Ball PBGA @ T
AMBIENT
= –40°C to +85°C –40 +115 °C
1
Internal voltage (V
DDINT
) regulator tolerance is –5% to +10% for all models.
2
See Ordering Guide on Page 63.
3
The internal voltage regulation feature is not available. External voltage regulation is required to ensure correct operation.
4
The ADSP-BF561 is 3.3 V tolerant (always accepts up to 3.6 V maximum V
IH
), but voltage compliance (on outputs, V
OH
) depends on the input V
DDEXT
, because V
OH
(maximum)
approximately equals V
DDEXT
(maximum). This 3.3 V tolerance applies to bidirectional and input only pins.
5
Applies to all signal pins.
Table 9 and Table 10 describe the timing requirements for the (VCO) operating frequencies, as described in Absolute Maxi-
ADSP-BF561 clocks (t
CCLK
= 1/f
CCLK
). Take care in selecting mum Ratings on Page 22. Table 11 describes phase-locked loop
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum operating conditions.
core clock, system clock, and Voltage Controlled Oscillator
Table 9. Core Clock (CCLK) Requirements—500 MHz and 533 MHz Speed Grade Models
1
Parameter Max Unit
f
CCLK
CCLK Frequency (V
DDINT
= 1.235 Vminimum)
2
533 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 1.1875 Vminimum) 500 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 1.045 Vminimum) 444 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 0.95 Vminimum) 350 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 0.855 Vminimum)
3
300 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 0.8 V minimum)
3
250 MHz
1
See Ordering Guide on Page 63.
2
External Voltage regulation is required on automotive grade models (see Ordering Guide on Page 63) to ensure correct operation.
3
Not applicable to automotive grade models. See Ordering Guide on Page 63.
Table 10. Core Clock (CCLK) Requirements—600 MHz Speed Grade Models
1
Parameter Max Unit
f
CCLK
CCLK Frequency (V
DDINT
= 1.2825 V minimum)
2
600 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 1.235 V minimum) 533 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 1.1875 V minimum) 500 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 1.045 V minimum) 444 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 0.95 V minimum) 350 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 0.855 V minimum) 300 MHz
f
CCLK
CCLK Frequency (V
DDINT
= 0.8 V minimum) 250 MHz
1
See Ordering Guide on Page 63.
2
External voltage regulator required to ensure proper operation at 600 MHz.
Rev. E | Page 20 of 64 | September 2009