Datasheet

ADSP-BF561
Table 8. Pin Descriptions (Continued)
Pin Name Type Function
Driver
Type
1
SPORT1
RSCLK1/PF30 I/O Sport1 Receive Serial Clock/Programmable Flag D
RFS1/PF24 I/O Sport1 Receive Frame Sync/Programmable Flag C
DR1PRI I Sport1 Receive Data Primary
DR1SEC/PF25 I/O Sport1 Receive Data Secondary/Programmable Flag C
TSCLK1/PF31 I/O Sport1 Transmit Serial Clock/Programmable Flag D
TFS1/PF21 I/O Sport1 Transmit Frame Sync/Programmable Flag C
DT1PRI/PF23 I/O Sport1 Transmit Data Primary/Programmable Flag C
DT1SEC/PF22 I/O Sport1 Transmit Data Secondary/Programmable Flag C
SPI
MOSI I/O Master Out Slave In C
MISO I/O Master In Slave Out (This pin should be pulled HIGH through a 4.7 kΩ resistor if booting via the SPI
port.)
C
SCK I/O SPI Clock D
UART
RX/PF27
TX/PF26
I/O
I/O
UART Receive/Programmable Flag
UART Transmit/Programmable Flag
C
C
JTAG
EMU
O Emulation Output C
TCK I JTAG Clock
TDO O JTAG Serial Data Out C
TDI I JTAG Serial Data In
TMS I JTAG Mode Select
TRST
I JTAG Reset (This pin should be pulled LOW if JTAG is not used.)
Clock
CLKIN
XTAL
I
O
Clock/Crystal Input (This pin needs to be at a level or clocking.)
Crystal Connection
Mode Controls
RESET
I Reset (This pin is always active during core power-on.)
NMI0 I Nonmaskable Interrupt Core A (This pin should be pulled LOW when not used.)
NMI1 I Nonmaskable Interrupt Core B (This pin should be pulled LOW when not used.)
BMODE1–0 I Boot Mode Strap (These pins must be pulled to the state required for the desired boot mode.)
SLEEP O Sleep C
BYPASS I PLL BYPASS Control (Pull-up or pull-down Required.)
Voltage Regulator
V
ROUT
1–0 O External FET Drive
Supplies
V
DDEXT
P Power Supply
V
DDINT
P Power Supply
GND G Power Supply Return
No Connection NC NC
1
Refer to Figure 30 on Page 41 to Figure 34 on Page 42.
Rev. E | Page 19 of 64 | September 2009