Datasheet

ADSP-BF561
PIN DESCRIPTIONS
ADSP-BF561 pin definitions are listed in Table 8. In order to
maintain maximum function and reduce package size and pin
count, some pins have multiple functions. In cases where pin
function is reconfigurable, the default state is shown in plain
text, while alternate functionality is shown in italics.
All pins are three-stated during and immediately after reset,
except the external memory interface, asynchronous memory
control, and synchronous memory control pins. These pins are
Table 8. Pin Descriptions
all driven high, with the exception of CLKOUT, which toggles at
the system clock rate. However if BR is active, the memory pins
are also three-stated.
All I/O pins have their input buffers disabled, with the exception
of the pins that need pull-ups or pull-downs if unused, as noted
in Table 8.
Pin Name Type Function
Driver
Type
1
EBIU
ADDR25–2 O Address Bus for Async/Sync Access A
DATA31–0 I/O Data Bus for Async/Sync Access A
ABE3–0
/SDQM3–0 O Byte Enables/Data Masks for Async/Sync Access A
BR I Bus Request (This pin should be pulled HIGH if not used.)
BG O Bus Grant A
BGH O Bus Grant Hang A
EBIU (ASYNC)
AMS3–0
O Bank Select A
ARDY I Hardware Ready Control (This pin should be pulled HIGH if not used.)
AOE
O Output Enable A
AWE O Write Enable A
ARE O Read Enable A
EBIU (SDRAM)
SRAS
O Row Address Strobe A
SCAS O Column Address Strobe A
SWE O Write Enable A
SCKE O Clock Enable A
SCLK0/CLKOUT O Clock Output Pin 0 B
SCLK1 O Clock Output Pin 1 B
SA10 O SDRAM A10 Pin A
SMS3–0
O Bank Select A
Rev. E | Page 17 of 64 | September 2009