Datasheet

Rev. E | Page 8 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
Event Control
The ADSP-BF538/ADSP-BF538F processors provide the user
with a very flexible mechanism to control the processing of
events. In the CEC, three registers are used to coordinate and
control events. Each register is 32 bits wide:
• CEC interrupt latch register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may also be written to clear (cancel) latched events. This
register may be read while in supervisor mode and may
only be written while in supervisor mode when the corre-
sponding IMASK bit is cleared.
• CEC interrupt mask register (IMASK) – The IMASK regis-
ter controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event, pre-
venting the processor from servicing the event even though
the event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. General-
purpose interrupts can be globally enabled and disabled
with the STI and CLI instructions, respectively.
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3 on Page 7.
• SIC interrupt mask registers (SIC_IMASKx) – These regis-
ters control the masking and unmasking of each peripheral
interrupt event. When a bit is set in these registers, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in these registers masks
the peripheral event, preventing the processor from servic-
ing the event.
• SIC interrupt status registers (SIC_ISRx) – As multiple
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
• SIC interrupt wake-up enable registers (SIC_IWRx) – By
enabling the corresponding bit in these registers, a periph-
eral can be configured to wake up the processor, should the
core be idled or in sleep mode when the event is generated.
(For more information, see Dynamic Power Management
on Page 13.)
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND
register contents are monitored by the SICs as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
DMA CONTROLLERS
The ADSP-BF538/ADSP-BF538F processors have two, inde-
pendent DMA controllers that support automated data transfers
with minimal overhead for the processor core. DMA transfers
can occur between the processor internal memories and any of
its DMA capable peripherals. Additionally, DMA transfers can
be accomplished between any of the DMA capable peripherals
and external devices connected to the external memory inter-
DMA10 Interrupt (SPORT3 Rx) IVG9
DMA11 Interrupt (SPORT3 Tx) IVG9
DMA5 Interrupt (SPI0) IVG10
DMA14 Interrupt (SPI1) IVG10
DMA15 Interrupt (SPI2) IVG10
DMA6 Interrupt (UART0 Rx) IVG10
DMA7 Interrupt (UART0 Tx) IVG10
DMA16 Interrupt (UART1 Rx) IVG10
DMA17 Interrupt (UART1 Tx) IVG10
DMA18 Interrupt (UART2 Rx) IVG10
DMA19 Interrupt (UART2 Tx) IVG10
Timer0, Timer1, Timer2 Interrupts IVG11
TWI0 Interrupt IVG11
TWI1 Interrupt IVG11
CAN Receive Interrupt IVG11
CAN Transmit Interrupt IVG11
Port F GPIO Interrupts A and B IVG12
MDMA0 Stream 0 Interrupt IVG13
MDMA0 Stream 1 Interrupt IVG13
MDMA1 Stream 0 Interrupt IVG13
MDMA1 Stream 1 Interrupt IVG13
Software Watchdog Timer IVG13
Table 3. System and Core Event Mapping (Continued)
Event Source
Core
Event Name