Datasheet

ADSP-BF538/ADSP-BF538F
Rev. E | Page 7 of 60 | November 2013
ensures that servicing of a higher priority event takes prece-
dence over servicing of a lower priority event. The controller
provides support for five different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Nonmaskable interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
• Exceptions – Events that occur synchronously to program
flow (the exception is taken before the instruction is
allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processors is saved on the
supervisor stack.
The ADSP-BF538/ADSP-BF538F processors’ event controllers
consist of two stages, the core event controller (CEC) and the
system interrupt controller (SIC). The core event controller
works with the system interrupt controller to prioritize and con-
trol all system events. Conceptually, interrupts from the
peripherals enter into the SIC and are then routed directly into
the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the processor.
Table 2 describes the inputs to the CEC, identifies their names
in the event vector table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The system interrupt controllers (SIC) provides the mapping
and routing of events from the many peripheral interrupt
sources to the prioritized general-purpose interrupt inputs of
the CEC. Although the ADSP-BF538/ADSP-BF538F processors
provide a default mapping, programs can alter the mappings
and priorities of interrupt events by writing the appropriate val-
ues into the interrupt assignment registers (SIC_IARx).
Table 3 describes the inputs into the SIC and the default map-
pings into the CEC.
Table 2. Core Event Controller (CEC)
Priority
(0 is Highest) Event Class EVT Entry
0Emulation/Test ControlEMU
1 Reset RST
2 Nonmaskable Interrupt NMI
3Exception EVX
4 Reserved —
5 Hardware Error IVHW
6Core Timer IVTMR
7 General Interrupt 7 IVG7
8 General Interrupt 8 IVG8
9 General Interrupt 9 IVG9
10 General Interrupt 10 IVG10
11 General Interrupt 11 IVG11
12 General Interrupt 12 IVG12
13 General Interrupt 13 IVG13
14 General Interrupt 14 IVG14
15 General Interrupt 15 IVG15
Table 3. System and Core Event Mapping
Event Source
Core
Event Name
PLL Wake-Up Interrupt IVG7
DMA Controller 0 Error IVG7
DMA Controller 1 Error IVG7
PPI Error Interrupt IVG7
SPORT0 Error Interrupt IVG7
SPORT1 Error Interrupt IVG7
SPORT2 Error Interrupt IVG7
SPORT3 Error Interrupt IVG7
SPI0 Error Interrupt IVG7
SPI1 Error Interrupt IVG7
SPI2 Error Interrupt IVG7
UART0 Error Interrupt IVG7
UART1 Error Interrupt IVG7
UART2 Error Interrupt IVG7
CAN Error Interrupt IVG7
Real-Time Clock Interrupts IVG8
DMA0 Interrupt (PPI) IVG8
DMA1 Interrupt (SPORT0 Rx) IVG9
DMA2 Interrupt (SPORT0 Tx) IVG9
DMA3 Interrupt (SPORT1 Rx) IVG9
DMA4 Interrupt (SPORT1 Tx) IVG9
DMA8 Interrupt (SPORT2 Rx) IVG9
DMA9 Interrupt (SPORT2 Tx) IVG9