Datasheet

Rev. E | Page 46 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
For information on the UART port receive and transmit opera-
tions, see the ADSP-BF538 Blackfin Processor Hardware
Reference.
JTAG Test and Emulation Port Timing
Table 40 and Figure 32 describe JTAG port operations.
Table 40. JTAG Port Timing
Parameter Min Max Unit
Timing Requirements
t
TCK
TCK Period 20 ns
t
STAP
TDI, TMS Setup Before TCK High 4 ns
t
HTAP
TDI, TMS Hold After TCK High 4 ns
t
SSYS
System Inputs Setup Before TCK High
1
4ns
t
HSYS
System Inputs Hold After TCK High
1
6ns
t
TRSTW
TRST Pulse Width
2
(Measured in TCK Cycles) 4 TCK
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 10 ns
t
DSYS
System Outputs Delay After TCK Low
3,4
012ns
1
System Inputs=ARDY, BMODE1–0, BR, DATA15–0, DR0PRI, DR0SEC, NMI, PF15–0, PPI_CLK, PPI3–0, SCL1–0, SDA1–0, SCK2–0, MISO2–0, MOSI2–0, SPI1SS,
SPI1SEL1, SPI2SS, SPI2SEL1, RX2–0, TX2–1, DT2PRI, DT2SEC, DR2PRI, DR2SEC, DT3PRI, DT3SEC, TSCLK3–0, DR3PRI, DR3SEC, RSCLK3–0, RFS3–0, TFS3–0,
CANTX, CANRX, RESET, PC9–4, GPW, and TMR2–0.
2
50 MHz maximum
3
System Outputs = AMS, AOE, ARE, AWE, ABE, BG, DATA15–0, PF15–0, PC9–5, PPI3-0, SPI1SS, SPI1SEL1, SCK2–0, MISO2–0, MOSI2–0, SPI2SS, SPI2SEL1, RX2–1,
TX2–0, DT2PRI, DT2SEC, DR2PRI, DR2SEC, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3–0, RFS3–0, TSCLK3–0, TFS3–0, CANTX, CLKOUT, SA10, SCAS, SCKE,
SMS, SRAS, SWE, and TMR2–0.
4
System open-drain outputs: CANRX (when configured as PC1) and PC4.
Figure 32. JTAG Port Timing
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS