Datasheet

ADSP-BF538/ADSP-BF538F
Rev. E | Page 45 of 60 | November 2013
Timer Cycle Timing
Table 39 and Figure 31 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
SCLK
/2) MHz.
Table 39. Timer Cycle Timing
Parameter Min Max Unit
Timing Characteristics
t
WL
Timer Pulse Width Input Low
1
1× t
SCLK
ns
t
WH
Timer Pulse Width Input High
1
1× t
SCLK
ns
t
TIS
Timer Input Setup Time Before CLKOUT Low
2
6.5 ns
t
TIH
Timer Input Hold Time After CLKOUT Low
2
–1 ns
Switching Characteristics
t
HTO
Timer Pulse Width Output 1× t
SCLK
(2
32
– 1) × t
SCLK
ns
t
TOD
Timer Output Delay After CLKOUT High 6 ns
1
The minimum pulse widths apply for TMRx signals in width capture and external clock modes.
2
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize timer flag inputs.
Figure 31. Timer Cycle Timing
CLKOUT
TMRx OUTPUT
TMRx INPUT
t
TIS
t
TIH
t
WH
,t
WL
t
TOD
t
HTO