Datasheet

ADSP-BF538/ADSP-BF538F
Rev. E | Page 43 of 60 | November 2013
Serial Peripheral Interface Ports—Slave Timing
Table 36 and Figure 28 describe SPI ports slave operations.
Table 36. Serial Peripheral Interface (SPI) Ports—Slave Timing
Parameter Min Max Unit
Timing Requirements
t
SPICHS
Serial Clock High Period 2 × t
SCLK
–1.5 ns
t
SPICLS
Serial Clock Low Period 2 × t
SCLK
–1.5 ns
t
SPICLK
Serial Clock Period 4 × t
SCLK
ns
t
HDS
Last SCKx Edge to SPIxSS Not Asserted 2 × t
SCLK
–1.5 ns
t
SPITDS
Sequential Transfer Delay 2 × t
SCLK
–1.5 ns
t
SDSCI
SPIxSS Assertion to First SCKx Edge 2 × t
SCLK
–1.5 ns
t
SSPID
Data Input Valid to SCKx Edge (Data Input Setup) 2.0 ns
t
HSPID
SCKx Sampling Edge to Data Input Invalid 2.0 ns
Switching Characteristics
t
DSOE
SPIxSS Assertion to Data Out Active 0 8 ns
t
DSDHI
SPIxSS Deassertion to Data High impedance 0 8 ns
t
DDSPID
SCKx Edge to Data Out Valid (Data Out Delay) 10 ns
t
HDSPID
SCKx Edge to Data Out Invalid (Data Out Hold) 0 ns
Figure 28. Serial Peripheral Interface (SPI) Ports—Slave Timing
t
SPICLK
t
HDS
t
SPITDS
t
SDSCI
t
SPICLS
t
SPICHS
t
DSOE
t
DDSPID
t
DDSPID
t
DSDHI
t
HDSPID
t
SSPID
t
DSDHI
t
HDSPID
t
DSOE
t
HSPID
t
SSPID
t
DDSPID
SPIxSS
(INPUT)
SPIxSCK
(INPUT)
SPIxMISO
(OUTPUT)
SPIxMOSI
(INPUT)
SPIxMISO
(OUTPUT)
SPIxMOSI
(INPUT)
CPHA = 1
CPHA = 0
t
HSPID