Datasheet

Rev. E | Page 42 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
Serial Peripheral Interface Ports—Master Timing
Table 35 and Figure 27 describe SPI ports master operations.
Table 35. Serial Peripheral Interface (SPI) Ports—Master Timing
Parameter Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid to SCKx Edge (Data Input Setup) 9.0 ns
t
HSPIDM
SCKx Sampling Edge to Data Input Invalid –1.5 ns
Switching Characteristics
t
SDSCIM
SPIxSELy Low to First SCKx edge 2 × t
SCLK
–1.5 ns
t
SPICHM
Serial Clock High Period 2 × t
SCLK
–1.5 ns
t
SPICLM
Serial Clock Low Period 2 × t
SCLK
–1.5 ns
t
SPICLK
Serial Clock Period 4 × t
SCLK
–1.5 ns
t
HDSM
Last SCKx Edge to SPIxSELy High 2 × t
SCLK
–1.5 ns
t
SPITDM
Sequential Transfer Delay 2 × t
SCLK
–1.5 ns
t
DDSPIDM
SCKx Edge to Data Out Valid (Data Out Delay) 5 ns
t
HDSPIDM
SCKx Edge to Data Out Invalid (Data Out Hold) –1.0 ns
Figure 27. Serial Peripheral Interface (SPI) Ports—Master Timing
t
SDSCIM
t
SPICLK
t
HDSM
t
SPITDM
t
SPICLM
t
SPICHM
t
HDSPIDM
t
HSPIDM
t
SSPIDM
SPIxSELy
(OUTPUT)
SPIxSCK
(OUTPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
CPHA = 1
CPHA = 0
t
DDSPIDM
t
HSPIDM
t
SSPIDM
t
HDSPIDM
t
DDSPIDM