Datasheet

Rev. E | Page 36 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
Parallel Peripheral Interface Timing
Table 30 and Figure 19, Figure 20, Figure 21, and Figure 22
describe parallel peripheral interface operations.
Table 30. Parallel Peripheral Interface Timing
Parameter Min Max Unit
Timing Requirements
t
PCLKW
PPI_CLK Width 6.0 ns
t
PCLK
PPI_CLK Period
1
15.0 ns
t
SFSPE
External Frame Sync Setup Before PPI_CLK 5.0 ns
t
HFSPE
External Frame Sync Hold After PPI_CLK 1.0 ns
t
SDRPE
Receive Data Setup Before PPI_CLK 2.0 ns
t
HDRPE
Receive Data Hold After PPI_CLK 4.0 ns
Switching Characteristics—GP Output and Frame Capture Modes
t
DFSPE
Internal Frame Sync Delay After PPI_CLK 10.0 ns
t
HOFSPE
Internal Frame Sync Hold After PPI_CLK 0.0 ns
t
DDTPE
Transmit Data Delay After PPI_CLK 10.0 ns
t
HDTPE
Transmit Data Hold After PPI_CLK 0.0 ns
1
PPI_CLK frequency cannot exceed f
SCLK
/2.
Figure 19. PPI GP Rx Mode with Internal Frame Sync Timing
Figure 20. PPI GP Rx Mode with External Frame Sync Timing
t
HDRPE
t
SDRPE
t
HOFSPE
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
t
DFSPE
t
PCLK
t
PCLKW
t
PCLK
t
SFSPE
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
t
HFSPE
t
HDRPE
t
SDRPE
t
PCLKW