Datasheet

ADSP-BF538/ADSP-BF538F
Rev. E | Page 35 of 60 | November 2013
Table 29. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Parameter Min Max Unit
Timing Requirement
t
WBR
BR Pulse Width 2 × t
SCLK
ns
Switching Characteristics
t
SD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable 4.5 ns
t
SE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable 4.5 ns
t
DBG
CLKOUT High to BG High Setup 3.6 ns
t
EBG
CLKOUT High to BG Deasserted Hold Time 3.6 ns
t
DBH
CLKOUT High to BGH High Setup 3.6 ns
t
EBH
CLKOUT High to BGH Deasserted Hold Time 3.6 ns
Figure 18. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
AMSx
CLKOUT
BG
BGH
BR
ADDR 19-1
ABE1-0
t
SD
t
SE
t
SD
t
SD
t
SE
t
SE
t
EBG
t
DBG
t
EBH
t
DBH
AWE
ARE
t
WBR