Datasheet

Rev. E | Page 34 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
External Port Bus Request and Grant Cycle Timing
Table 28 and Table 29 on Page 35 and Figure 17 and Figure 18
on Page 35 describe external port bus request and grant cycle
operations for synchronous and for asynchronous BR
.
Table 28. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter Min Max Unit
Timing Requirements
t
BS
BR Setup to Falling Edge of CLKOUT 4.6 ns
t
BH
Falling Edge of CLKOUT to BR Deasserted Hold Time 1.0 ns
Switching Characteristics
t
SD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable 4.5 ns
t
SE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable 4.5 ns
t
DBG
CLKOUT High to BG High Setup 4.0 ns
t
EBG
CLKOUT High to BG Deasserted Hold Time 4.0 ns
t
DBH
CLKOUT High to BGH High Setup 4.0 ns
t
EBH
CLKOUT High to BGH Deasserted Hold Time 4.0 ns
Figure 17. External Port Bus Request and Grant Cycle Timing with Synchronous BR
AMSx
CLKOUT
BG
BGH
BR
ADDR 19-1
ABE1-0
t
BH
t
BS
t
SD
t
SE
t
SD
t
SD
t
SE
t
SE
t
EBG
t
DBG
t
EBH
t
DBH
AWE
ARE