Datasheet

Rev. E | Page 32 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
Table 26. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Parameter Min Max Unit
Timing Requirements
t
DANW
ARDY Negated Delay from AMSx Asserted
1
(S + WA – 2) × t
SCLK
ns
t
HAA
ARDY Asserted Hold After ARE Negated 0.0 ns
Switching Characteristics
t
DDAT
DATA15–0 Disable After CLKOUT 6.0 ns
t
ENDAT
DATA15–0 Enable After CLKOUT 1.0 ns
t
DO
Output Delay After CLKOUT
2
6.0 ns
t
HO
Output Hold After CLKOUT
2
0.8 ns
1
S = number of programmed setup cycles, WA = number of programmed write access cycles.
2
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
Figure 15. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
SETUP
2 CYCLES
PROGRAMMED
WRITE ACCESS
2 CYCLES
ACCESS
EXTENDED
2 CYCLES
HOLD
1 CYCLE
t
DO
t
HO
CLKOUT
AMSx
ABE1–0
ADDR19–1
AWE
ARDY
DATA 15–0
t
DO
t
DDAT
t
ENDAT
t
HO
t
DANW
t
HAA