Datasheet

ADSP-BF538/ADSP-BF538F
Rev. E | Page 31 of 60 | November 2013
Asynchronous Memory Write Cycle Timing
Table 25 and Table 26 on Page 32 and Figure 14 and Figure 15
on Page 32 describe asynchronous memory write cycle opera-
tions for synchronous and for asynchronous ARDY.
Table 25. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Parameter Min Max Unit
Timing Requirements
t
SARDY
ARDY Setup Before the Falling Edge of CLKOUT 4.0 ns
t
HARDY
ARDY Hold After the Falling Edge of CLKOUT 0.0 ns
Switching Characteristics
t
DDAT
DATA15–0 Disable After CLKOUT 6.0 ns
t
ENDAT
DATA15–0 Enable After CLKOUT 1.0 ns
t
DO
Output Delay After CLKOUT
1
6.0 ns
t
HO
Output Hold After CLKOUT
1
0.8 ns
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
Figure 14. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
SETUP
2 CYCLES
PROGRAMMED
WRITE ACCESS
2 CYCLES
ACCESS
EXTEND
1 CYCLE
HOLD
1 CYCLE
t
DO
t
HO
CLKOUT
AMSx
ABE1–0
ADDR19–1
AWE
DATA 15–0
t
DO
t
SARDY
t
DDAT
t
ENDAT
t
HO
t
HARDY
t
HARDY
ARDY
t
SARDY