Datasheet

Rev. E | Page 30 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
Table 24. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Parameter Min Max Unit
Timing Requirements
t
SDAT
DATA15–0 Setup Before CLKOUT 2.1 ns
t
HDAT
DATA15–0 Hold After CLKOUT 0.8 ns
t
DANR
ARDY Negated Delay from AMSx Asserted
1
(S + RA – 2)  t
SCLK
ns
t
HAA
ARDY Asserted Hold After ARE Negated 0.0 ns
Switching Characteristics
t
DO
Output Delay After CLKOUT
2
6.0 ns
t
HO
Output Hold After CLKOUT
2
0.8 ns
1
S = number of programmed setup cycles, RA = number of programmed read access cycles.
2
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
Figure 13. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
SETUP
2 CYCLES
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
t
DO
t
HO
t
DO
t
DANR
t
SDAT
t
HDAT
CLKOUT
AMSx
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA 15–0
t
HO
t
HAA