Datasheet

ADSP-BF538/ADSP-BF538F
Rev. E | Page 29 of 60 | November 2013
Asynchronous Memory Read Cycle Timing
Table 23 and Table 24 on Page 30 and Figure 12 and Figure 13
on Page 30 describe asynchronous memory read cycle opera-
tions for synchronous and for asynchronous ARDY.
Table 23. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter Min Max Unit
Timing Requirements
t
SDAT
DATA15–0 Setup Before CLKOUT 2.1 ns
t
HDAT
DATA15–0 Hold After CLKOUT 0.8 ns
t
SARDY
ARDY Setup Before the Falling Edge of CLKOUT 4.0 ns
t
HARDY
ARDY Hold After the Falling Edge of CLKOUT 0.0 ns
Switching Characteristics
t
DO
Output Delay After CLKOUT
1
6.0 ns
t
HO
Output Hold After CLKOUT
1
0.8 ns
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
Figure 12. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
t
SARDY
t
HARDY
t
SARDY
t
HARDY
SETUP
2 CYCLES
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
t
DO
t
HO
t
DO
t
SDAT
t
HDAT
CLKOUT
AMSx
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA 15–0
t
HO