Datasheet

Rev. E | Page 28 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
TIMING SPECIFICATIONS
Component specifications are subject to change
with PCN notice.
Clock and Reset Timing
Table 21 and Figure 10 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 27, combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks that exceed maximum operating conditions.
Table 21. Clock and Reset Timing
Parameter Min Max Unit
Timing Requirements
f
CKIN
CLKIN Frequency (Commercial/ Industrial Models)
1, 2, 3, 4
10 50 MHz
t
CKINL
CLKIN Low Pulse
1
8ns
t
CKINH
CLKIN High Pulse
1
8ns
t
WRST
RESET Asserted Pulse Width Low
5
11 × t
CKIN
ns
t
NOBOOT
RESET Deassertion to First External Access Delay
6
3 × t
CKIN
5 × t
CKIN
ns
1
Applies to PLL bypass mode and PLL nonbypass mode.
2
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
VCO
, f
CCLK
, and f
SCLK
settings discussed in Table 11 on Page 24 through
Table 16 on Page 26.
3
The t
CKIN
period (see Figure 10) equals 1/f
CKIN
.
4
If the DF bit in the PLL_CTL register is set, the minimum f
CKIN
specification is 24 MHz for commercial/industrial models.
5
Applies after power-up sequence is complete. See Table 22 and Figure 11 for power-up reset timing.
6
Applies when processor is configured in No Boot Mode (BMODE2-0 = b#000).
Figure 10. Clock and Reset Timing
Table 22. Power-Up Reset Timing
Parameter Min Max Unit
Timing Requirement
t
RST_IN_PWR
RESET Deasserted after the V
DDINT
, V
DDEXT
, V
DDRTC
, and CLKIN Pins are Stable and Within
Specification
3500 × t
CKIN
ns
In Figure 11, V
DD_SUPPLIES
is V
DDINT
, V
DDEXT
, V
DDRTC
Figure 11. Power-Up Reset Timing
CLKIN
t
WRST
t
CKIN
t
CKINL
t
CKINH
RESET
t
NOBOOT
RESET
t
RST_IN_PWR
CLKIN
V
DD_SUPPLIES