Datasheet

ADSP-BF538/ADSP-BF538F
Rev. E | Page 25 of 60 | November 2013
ELECTRICAL CHARACTERISTICS
System designers should refer to Estimating Power for the
ADSP-BF538/BF539 Blackfin Processors (EE-298), which pro-
vides detailed information for optimizing designs for lowest
power. All topics discussed in this section are described in detail
in EE-298. Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. Electrical Characteristics on Page 25 shows the
current dissipation for internal circuitry (V
DDINT
). I
DDDEEPSLEEP
specifies static power dissipation as a function of voltage
(V
DDINT
) and temperature (see Table 15), and I
DDINT
specifies the
total power specification for the listed test conditions, including
the dynamic component as a function of voltage (V
DDINT
) and
frequency (Table 17).
The dynamic component is also subject to an Activity Scaling
Factor (ASF) which represents application code running on the
processor (Table 16).
Parameter
1
1
Specifications subject to change without notice.
Test Conditions Min Typ Max Unit
V
OH
High Level Output Voltage
2
2
Applies to output and bidirectional pins.
V
DDEXT
= +3.0 V, I
OH
= –0.5 mA 2.4 V
V
OL
Low Level Output Voltage
2
V
DDEXT
= 3.0 V, I
OL
= 2.0 mA 0.4 V
I
IH
High Level Input Current
3
3
Applies to input pins except JTAG inputs.
V
DDEXT
= Maximum, V
IN
= V
DD
Maximum 10.0 μA
I
IHP
High Level Input Current JTAG
4
4
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
V
DDEXT
= Maximum, V
IN
= V
DD
Maximum 50.0 μA
I
IL
Low Level Input Current
3
V
DDEXT
= Maximum, V
IN
= 0 V 10.0 μA
I
OZH
Three-State Leakage Current
5
5
Applies to three-statable pins.
V
DDEXT
= Maximum, V
IN
= V
DD
Maximum 10.0 μA
I
OZL
Three-State Leakage Current
5
V
DDEXT
= Maximum, V
IN
= 0 V 10.0 μA
C
IN
Input Capacitance
6, 7
6
Applies to all signal pins.
7
Guaranteed, but not tested.
f
CCLK
= 1 MHz, T
AMBIENT
= 25°C, V
IN
= 2.5 V 4 8 pF
I
DDDEEPSLEEP
8
8
See the ADSP-BF538/538F Blackfin Processor Hardware Reference for definitions of sleep, deep sleep, and hibernate operating modes.
V
DDINT
Current in Deep Sleep Mode V
DDINT
= 1.0 V, f
CCLK
= 0 MHz, T
J
= 25°C,
ASF = 0.00
7.5 mA
I
DDSLEEP
V
DDINT
Current in Sleep Mode V
DDINT
= 0.8 V, T
J
= 25°C, SCLK = 25 MHz 10 mA
I
DD-TYP
V
DDINT
Current V
DDINT
= 1.14 V, f
CCLK
= 400 MHz, T
J
= 25°C 130 mA
I
DD-TYP
V
DDINT
Current V
DDINT
= 1.2 V, f
CCLK
= 500 MHz, T
J
= 25°C 168 mA
I
DD-TYP
V
DDINT
Current V
DDINT
= 1.2 V, f
CCLK
= 533 MHz, T
J
= 25°C 180 mA
I
DDHIBERNATE
8
V
DDEXT
Current in Hibernate State V
DDEXT
= 3.6 V, CLKIN = 0 MHz, T
J
= Max,
voltage regulator off (V
DDINT
= 0 V)
50 100 A
I
DDRTC
V
DDRTC
Current V
DDRTC
= 3.3 V, T
J
= 25C 20 A
I
DDDEEPSLEEP
8
V
DDINT
Current in Deep Sleep Mode f
CCLK
= 0 MHz 6 Table 15 mA
I
DDINT
9
9
See Table 16 for the list of I
DDINT
power vectors covered by various Activity Scaling Factors (ASF).
V
DDINT
Current f
CCLK
> 0 MHz I
DDDEEPSLEEP
+
(Table 17  ASF)
mA