Datasheet

Rev. E | Page 24 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
The following tables describe the voltage/frequency require-
ments for the ADSP-BF538/ADSP-BF538F processor clocks.
Take care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock (Table 11 and Table 12) and
system clock (Table 14) specifications. Table 13 describes
phase-locked loop operating conditions.
Table 11. Core Clock (CCLK) Requirements — 400 MHz Models
Parameter
Internal Regulator
Setting Max Unit
f
CCLK
CLK Frequency (V
DDINT
= 1.14 V Minimum) 1.20 V 400 MHz
f
CCLK
CLK Frequency (V
DDINT
= 1.045 V Minimum) 1.10 V 364 MHz
f
CCLK
CLK Frequency (V
DDINT
= 0.95 V Minimum) 1.00 V 333 MHz
f
CCLK
CLK Frequency (V
DDINT
= 0.85 V Minimum) 0.90 V 280 MHz
f
CCLK
CLK Frequency (V
DDINT
= 0.8 V Minimum) 0.85 V 250 MHz
Table 12. Core Clock (CCLK) Requirements — 533 MHz Models
Parameter Internal Regulator Setting Max Unit
f
CCLK
Core Clock Frequency (V
DDINT
= 1.2 V Minimum) 1.25 V 533 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 1.14 V Minimum) 1.20 V 500 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 1.045 V Minimum) 1.10 V 444 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.95 V Minimum) 1.00 V 400 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.85 V Minimum) 0.95 V 333 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.8 V Minimum) 0.85 V 250 MHz
Table 13. Phase-Locked Loop Operating Conditions
Parameter Min Max Unit
f
VCO
Voltage Controlled Oscillator (VCO) Frequency 50 Max f
CCLK
MHz
Table 14. System Clock (SCLK) Requirements
Parameter
1
Max Unit
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
 1.14 V) 133
2
MHz
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
 1.14 V) 100 MHz
1
t
SCLK
(= 1/f
SCLK
) must be greater than or equal to t
CCLK
.
2
Guaranteed to t
SCLK
= 7.5 ns. See Table 27 on page 33.