Datasheet

Rev. E | Page 22 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
PF7/PPI12/SPI0SEL7 I/O GPIO/PPI12/SPI0 Slave Select Enable 7 C
PF8/PPI11 I/O GPIO/PPI11 C
PF9/PPI10 I/O GPIO/PPI10 C
PF10/PPI9 I/O GPIO/PPI9 C
PF11/PPI8 I/O GPIO/PPI8 C
PF12/PPI7 I/O GPIO/PPI7 C
PF13/PPI6 I/O GPIO/PPI6 C
PF14/PPI5 I/O GPIO/PPI5 C
PF15/PPI4 I/O GPIO/PPI4 C
Real-Time Clock
RTXI I RTC Crystal Input (This pin should be pulled low when not used.)
RTXO O RTC Crystal Output (Does not three-state in hibernate.)
JTAG Port
TCK I JTAG Clock
TDO O JTAG Serial Data Out C
TDI I JTAG Serial Data In
TMS I JTAG Mode Select
TRST
I JTAG Reset (This pin should be pulled low if the JTAG port will not be used.)
EMU
O Emulation Output C
Clock
CLKIN I Clock/Crystal Input
XTAL O Crystal Output
Mode Controls
RESET
IReset
NMI
I Nonmaskable Interrupt (This pin should be pulled high when not used.)
BMODE1–0 I Boot Mode Strap (These pins must be pulled to the state required for the
desired boot mode.)
Voltage Regulator
VROUT1–0 O External FET Drive 0 (These pins should be left unconnected when
not used and are driven high during hibernate.)
GPW
I 5 V General-Purpose Regulator Wake-Up (This pin should be pulled high
when not used.)
Supplies
V
DDEXT
PI/O Power Supply
V
DDINT
P Internal Power Supply
V
DDRTC
P Real-Time Clock Power Supply (This pin should be connected to V
DDEXT
when not used and should remain powered at all times.)
GND G Ground
1
Refer to Figure 33 on Page 47 to Figure 43 on Page 49.
2
This pin is 5 V-tolerant when configured as an input and an open-drain when configured as an output; therefore, only the VOL curves in Figure 37 on Page 48 and Figure 38
on Page 48 and the Fall Time curves in Figure 50 on Page 51 and Figure 51 on Page 51 apply when configured as an output.
Table 10. Pin Descriptions (Continued)
Pin Name I/O Function Driver Type
1