Datasheet

Rev. E | Page 20 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
2-Wire Interface Port These pins are open-drain and require a pull-up resistor. See version 2.1
of the I
2
C specification for proper resistor values.
SDA0 I/O 5 V TWI0 Serial Data E
SCL0 I/O 5 V TWI0 Serial Clock E
SDA1 I/O 5 V TWI1 Serial Data E
SCL1 I/O 5 V TWI1 Serial Clock E
Serial Port0
RSCLK0 I/O SPORT0 Receive Serial Clock D
RFS0 I/O SPORT0 Receive Frame Sync C
DR0PRI I SPORT0 Receive Data Primary
DR0SEC I SPORT0 Receive Data Secondary
TSCLK0 I/O SPORT0 Transmit Serial Clock D
TFS0 I/O SPORT0 Transmit Frame Sync C
DT0PRI O SPORT0 Transmit Data Primary C
DT0SEC O SPORT0 Transmit Data Secondary C
Serial Port1
RSCLK1 I/O SPORT1 Receive Serial Clock D
RFS1 I/O SPORT1 Receive Frame Sync C
DR1PRI I SPORT1 Receive Data Primary
DR1SEC I SPORT1 Receive Data Secondary
TSCLK1 I/O SPORT1 Transmit Serial Clock D
TFS1 I/O SPORT1 Transmit Frame Sync C
DT1PRI O SPORT1 Transmit Data Primary C
DT1SEC O SPORT1 Transmit Data Secondary C
SPI0 Port
MOSI0 I/O SPI0 Master Out Slave In C
MISO0 I/O SPI0 Master In Slave Out (This pin should always be pulled high through
a 4.7 k resistor if booting via the SPI port.)
C
SCK0 I/O SPI0 Clock D
UART0 Port
RX0 I UART0 Receive
TX0 O UART0 Transmit C
PPI Port
PPI3–0 I/O PPI3–0 C
PPI_CLK/TMRCLK I PPI Clock/External Timer Reference
Port C: Controller Area Network/GPIO
CANTX/PC0 I/O 5 V CAN Transmit/GPIO C
CANRX/PC1 I/OD 5 V CAN Receive/GPIO C
2
PC[9-5]
PC4
I/O
I/OD 5 V
GPIO
GPIO
C
C
2
Table 10. Pin Descriptions (Continued)
Pin Name I/O Function Driver Type
1