Datasheet

ADSP-BF538/ADSP-BF538F
Rev. E | Page 19 of 60 | November 2013
PIN DESCRIPTIONS
The ADSP-BF538/ADSP-BF538F processors pin definitions are
listed in Table 10.
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins. These pins are all
driven high, with the exception of CLKOUT, which toggles at
the system clock rate. If BR
is active (whether or not RESET is
asserted), the memory pins are also three-stated. All unused I/O
pins have their input buffers disabled with the exception of the
pins that need pull-ups or pull-downs, as noted in the table.
During hibernate, all outputs are three-stated unless otherwise
noted in Table 10.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.
Table 10. Pin Descriptions
Pin Name I/O Function Driver Type
1
Memory Interface
ADDR19–1 O Address Bus for Async/Sync Access A
DATA15–0 I/O Data Bus for Async/Sync Access A
ABE1–0
/SDQM1–0 O Byte Enables/Data Masks for Async/Sync Access A
BR
I Bus Request (This pin should be pulled high when not used.)
BG
OBus Grant A
BGH
O Bus Grant Hang A
Asynchronous Memory Control
AMS3–0
O Bank Select (Require pull-ups if hibernate is used.) A
ARDY I Hardware Ready Control
AOE
O Output Enable A
ARE
ORead Enable A
AWE
OWrite Enable A
Flash Control
FCE
I Flash Enable (This pin is internally connected to GND on the ADSP-BF538.)
FRESET
I Flash Reset (This pin is internally connected to GND on the ADSP-BF538.)
Synchronous Memory Control
SRAS
O Row Address Strobe A
SCAS
O Column Address Strobe A
SWE
OWrite Enable A
SCKE O Clock Enable (This pin must be pulled low through a 10 k resistor if
hibernate state is used and SDRAM contents need to be preserved during
hibernate.)
A
CLKOUT O Clock Output B
SA10 O A10 Pin A
SMS
O Bank Select A
Timers
TMR0 I/O Timer 0 C
TMR1/PPI_FS1 I/O Timer 1/PPI Frame Sync1 C
TMR2/PPI_FS2 I/O Timer 2/PPI Frame Sync2 C