Datasheet

Rev. E | Page 16 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
BOOTING MODES
The ADSP-BF538/ADSP-BF538F processors have three mecha-
nisms (listed in Table 9) for automatically loading internal L1
instruction memory after a reset. A fourth mode is provided to
execute from external memory, bypassing the boot sequence.
The BMODE pins of the reset configuration register, sampled
during power-on resets and software initiated resets, implement
the following modes:
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit or 16-bit external flash memory – The 8-bit
flash boot routine located in boot ROM memory space is
set up using asynchronous memory bank 0. For
ADSP-BF538F processors, the on-chip flash is booted if
FCE
is connected to AMS0. All configuration settings are
set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit
addressable, or Atmel AT45DB041, AT45DB081, or
AT45DB161) connected to SPI0– SPI0 uses the PF2 output
pin to select a single SPI EEPROM/flash device, submits a
read command and successive address bytes (0x00) until a
valid 8-, 16-, or 24-bit, or Atmel addressable device is
detected, and begins clocking data into the processor at the
beginning of L1 instruction memory.
• Boot from SPI host device connected to SPI0 – The Black-
fin processor operates in SPI slave mode and is configured
to receive the bytes of the LDR file from an SPI host (mas-
ter) agent. To hold off the host device from transmitting
while the boot ROM is busy, the Blackfin processor asserts
a GPIO pin, called host wait (HWAIT), to signal the host
device not to send any more bytes until the flag is deas-
serted. The flag is chosen by the user and this information
is transferred to the Blackfin processor via bits 10:5 of the
FLAG header in the LDR image.
For each of the boot modes, a 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
To augment the boot modes, a secondary software loader is pro-
vided that adds additional booting mechanisms. This secondary
loader provides the capability to boot from 16-bit flash memory,
fast flash, variable baud rate, and other sources. In all boot
modes except bypass, program execution starts from on-chip L1
memory address 0xFFA0 0000.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU plus
two load/store plus two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program-
ming model.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore
®
Embed-
ded Studio and/or VisualDSP++
®
), evaluation products,
emulators, and a wide variety of software add-ins.
Table 9. Booting Modes
BMODE1–0 Description
00 Execute from 16-Bit External Memory
(Bypass Boot ROM)
01 Boot from 8-Bit or 16-Bit Flash, or
Boot from On-Chip Flash (ADSP-BF538F Only)
10 Boot from SPI Serial Master Connected to SPI0
11 Boot from SPI Serial Slave EEPROM/Flash
(8-,16-, or 24-Bit Address Range, or Atmel
AT45DB041, AT45DB081, or AT45DB161 Serial Flash)
Connected to SPI0