Datasheet

ADSP-BF538/ADSP-BF538F
Rev. E | Page 15 of 60 | November 2013
If an external clock is used, it should be a TTL-compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF538/ADSP-BF538F proces-
sors include an on-chip oscillator circuit, an external crystal
may be used. For fundamental frequency operation, use the cir-
cuit shown in Figure 7. A parallel-resonant, fundamental
frequency, microprocessor-grade crystal is connected across the
CLKIN and XTAL pins. The on-chip resistance between CLKIN
and the XTAL pin is in the 500 kW range. Further parallel resis-
tors are typically not recommended. The two capacitors and the
series resistor, shown in Figure 7, fine tune the phase and ampli-
tude of the sine frequency. The capacitor and resistor values,
shown in Figure 7, are typical values only. The capacitor values
are dependent upon the crystal manufacturer's load capacitance
recommendations and the physical PCB layout. The resistor
value depends on the drive level specified by the crystal manu-
facturer. System designs should verify the customized values
based on careful investigation on multiple devices over the
allowed temperature range.
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 7.
As shown in Figure 8, the core clock (CCLK) and system
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user programmable 0.5 to 64 multiplica-
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10, but it can be
modified by a software instruction sequence. On-the-fly fre-
quency changes can be effected by simply writing to the
PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1
through 15.
Table 7 illustrates typical system clock ratios:
The maximum frequency of the system clock is f
SCLK
. Note that
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f
SCLK
. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
Note that when the SSEL value is changed, it will affect all the
peripherals that derive their clock signals from the SCLK signal.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 8. This programmable core clock capability is useful for
fast core frequency modifications.
Figure 7. External Crystal Connections
CLKIN
CLKOUT
XTAL
EN
18pF* 18pF*
FOR OVERTONE
OPERATION ONLY
V
DDEXT
TO PLL CIRCUITRY
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
Blackfin
700:
0: *
1M:
Figure 8. Frequency Modification Methods
Table 7. Example System Clock Ratios
Signal Name
SSEL3–0
Divider Ratio
VCO/SCLK
Example Frequency Ratios (MHz)
VCO SCLK
0001 1:1 100 100
0110 6:1 300 50
1010 10:1 500 50
Table 8. Core Clock Ratios
Signal Name
CSEL1–0
Divider Ratio
VCO/CCLK
Example Frequency Ratios
VCO CCLK
00 1:1 300 300
01 2:1 300 150
10 4:1 500 125
11 8:1 200 25
PLL
0.5u
TO 64u
÷1:15
÷1,2,4,8
VCO
SCLK d
CCLK
SCLK d
133MHz
CLKIN
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
CCLK
SCLK