Datasheet

Rev. E | Page 14 of 60 | November 2013
ADSP-BF538/ADSP-BF538F
internal logic except for the RTC logic. The 3.3 V V
DDEXT
power
domain supplies all the I/O except for the RTC crystal. There
are no sequencing requirements for the various power domains.
The V
DDRTC
should either be connected to a battery (if the RTC
is to operate while the rest of the chip is powered down) or
should be connected to the V
DDEXT
plane on the board. The
V
DDRTC
should remain powered when the processor is in hiber-
nate state, and should also be powered even if the RTC
functionality is not being used in an application.
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The dynamic power management feature of the processor
allows both the processor’s input voltage (V
DDINT
) and clock fre-
quency (f
CCLK
) to be dynamically controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as
where:
f
CCLKNOM
is the nominal core clock frequency.
f
CCLKRED
is the reduced core clock frequency.
V
DDINTNOM
is the nominal internal supply voltage.
V
DDINTRED
is the reduced internal supply voltage.
t
NOM
is the duration running at f
CCLKNOM
.
t
RED
is the duration running at f
CCLKRED
.
The power savings factor is calculated as
VOLTAGE REGULATION
The Blackfin processors provide an on-chip voltage regulator
that can generate appropriate V
DDINT
voltage levels from the
V
DDEXT
supply. See Operating Conditions on Page 23 for regula-
tor tolerances and acceptable V
DDEXT
ranges for specific models.
The regulator controls the internal logic voltage levels and is
programmable with the voltage regulator control register
(VR_CTL) in increments of 50 mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while I/O power (V
DDRTC
,
V
DDEXT
) is still supplied. While in the hibernate state, I/O power
is still being applied, eliminating the need for external buffers.
The voltage regulator can be activated from this power-down
state either through an RTC wake-up, a CAN wake-up, a
general-purpose wake-up, or by asserting RESET
, all of which
will then initiate a boot sequence. The regulator can also be dis-
abled and bypassed at the user’s discretion.
Voltage Regulator Layout Guidelines
Regulator external component placement, board routing, and
bypass capacitors all have a significant effect on noise injected
into the other analog circuits on-chip. The VROUT1–0 traces
and voltage regulator external components should be consid-
ered as noise sources when doing board layout and should not
be routed or placed near sensitive circuits or components on the
board. All internal and I/O power supplies should be well
bypassed with bypass capacitors placed as close to the
ADSPBF538/ADSP-BF538F processors as possible.
For further details on the on-chip voltage regulator and related
board design guidelines, see the Switching Regulator Design
Considerations for ADSP-BF533 Blackfin Processor (EE-228)
applications note on the Analog Devices website
(www.analog.com)—use site search on “EE-228”.
CLOCK SIGNALS
The ADSP-BF538/ADSP-BF538F processors can be clocked by
an external crystal, a sine wave input, or a buffered, shaped
clock derived from an external clock oscillator.
Table 6. Power Domains
Power Domain V
DD
Range
RTC Crystal I/O and Logic V
DDRTC
All Internal Logic Except RTC V
DDINT
All I/O Except RTC V
DDEXT
Power Savings Factor
f
CCLKRED
f
CCLKNOM
--------------- --------
V
DDINTRED
V
DDINTNOM
----------------- -----------


2

t
RED
t
NOM
------------





=
% Power Savings 1 Power Savings Factor–100%=
Figure 6. Voltage Regulator Circuit
V
DDEXT
(LOW-INDUCTANCE)
V
DDINT
VR
OUT
100μF
VR
OUT
GND
SHORT AND LOW-
INDUCTANCE WIRE
V
DDEXT
+
+
+
100μF
100μF
10μF
LOW ESR
100nF
SET OF DECOUPLING
CAPACITORS
FDS9431A
ZHCS1000
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
10μH