Datasheet

ADSP-BF538/ADSP-BF538F
Rev. E | Page 11 of 60 | November 2013
UART PORTS
The ADSP-BF538/ADSP-BF538F processors incorporate three
full-duplex universal asynchronous receiver/transmitter
(UART) ports, which are fully compatible with PC standard
UARTs. The UART ports provide a simplified UART interface
to other peripherals or hosts, supporting full-duplex, DMA sup-
ported, asynchronous transfers of serial data. The UART ports
include support for 5 data bits to 8 data bits, 1 stop bit or 2 stop
bits, and none, even, or odd parity. The UART ports support
two modes of operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
Each UART port’s baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Supporting bit rates ranging from (f
SCLK
/1,048,576) to
(f
SCLK
/16) bits per second.
• Supporting data formats from 7 to 12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
Each UART port’s clock rate is calculated as:
where the 16-bit UART_Divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant 8 bits).
In conjunction with the general-purpose timer functions, auto-
baud detection is supported on UART0.
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA
®
) Serial Infrared
Physical Layer Link Specification (SIR) protocol.
GENERAL-PURPOSE PORTS
The ADSP-BF538/ADSP-BF538F processors have up to 54 gen-
eral-purpose I/O pins that are multiplexed with other
peripherals. They are arranged into Ports C, D, E, and F as
shown in Table 4.
The general-purpose I/O pins may be individually controlled by
manipulation of the control and status registers. These pins may
be polled to determine their status.
• GPIO direction control register – Specifies the direction of
each individual GPIO pin as input or output.
• GPIO control and status registers – The processor employs
a “write one to modify” mechanism that allows any combi-
nation of individual GPIO to be modified in a single
instruction, without affecting the level of any other GPIO.
Four control registers and a data register are provided for
each GPIO port. One register is written in order to set
GPIO values, one register is written in order to clear GPIO
values, one register is written in order to toggle GPIO val-
ues, and one register is written in order to specify a GPIO
input or output. Reading the GPIO data allows software to
determine the state of the input GPIO pins.
In addition to the GPIO function described above, the 16 Port F
pins can be individually configured to generate interrupts.
• GPIO pin interrupt mask registers – The two GPIO pin
interrupt mask registers allow each individual PFx pin to
function as an interrupt to the processor. Similar to the two
GPIO control registers that are used to set and clear indi-
vidual GPIO pin values, one GPIO pin interrupt mask
register sets bits to enable interrupt function, and the other
GPIO pin interrupt mask register clears bits to disable
interrupt function. PFx pins defined as inputs can be con-
figured to generate hardware interrupts, while output PFx
pins can be triggered by software interrupts.
• GPIO pin interrupt sensitivity registers – The two GPIO
pin interrupt sensitivity registers specify whether individ-
ual PFx pins are level- or edge-sensitive and specify—if
edge-sensitive—whether just the rising edge or both the ris-
ing and falling edges of the signal are significant. One
register selects the type of sensitivity, and one register
selects which edges are significant for edge-sensitivity.
PARALLEL PERIPHERAL INTERFACE
The ADSP-BF538/ADSP-BF538F processors provide a parallel
peripheral interface (PPI) that can connect directly to parallel
ADC and DAC converters, video encoders and decoders, and
other general-purpose peripherals. The PPI consists of a dedi-
cated input clock pin, up to 3 frame synchronization pins, and
up to 16 data pins. The input clock supports parallel data rates at
up to f
SCLK
/2 MHz, and the synchronization signals can be con-
figured as either inputs or outputs.
UART Clock Rate
f
SCLK
16 UART_Divisor
--------------- -------------------------------- ----
=
Table 4. GPIO Ports
Peripheral Alternate GPIO Port Function
PPI GPIO Port F15–3
SPORT2 GPIO Port E7–0
SPORT3 GPIO Port E15–8
SPI0 GPIO Port F7–0
SPI1 GPIO Port D4–0
SPI2 GPIO Port D9–5
UART1 GPIO Port D11–10
UART2 GPIO Port D13–12
CAN GPIO Port C1–0
GPIO GPIO Port C9–4
1
1
These pins are GPIO only and cannot be reconfigured through software. PC1
and PC4 are open-drain when configured as GPIO outputs.